Design And Implement Of Synchronization System In Single-carrier Mode Based On DTMB Standard

In recent years,the terrestrial digital TV technology has been widely concerned.Digital TV terrestrial broadcasting system needs a very high synchronization performance,because it faces the complicated and changeable terrestrial channel.So the design of synchronization system is of vital importance for the digital receiver,and the performance of the synchronization system is directly related to the quality of the receiver,which still need to research further.In the current field of communication,synchronization has become a hot topic.Frame structure of the DTMB single carrier system is made full use of.Frame synchronization,carrier synchronization and sampling synchronization algorithm are studied in depth.A DTMB single carrier system synchronization scheme is designed and carried out in FPGA.The main work is embodied in the following four aspects.First of all,the DTMB transmission system is introduced in detail.The sender and receiver of the DTMB single carrier system,and the characteristics of the system frame structure are studied.And the DTMB single carrier system synchronization technology is studied.The cause of occurring of various synchronization and the influence of various synchronization errors have been analyzed,which further clarify the importance of synchronization for the DTMB single carrier systems.Secondly,on the basis of further study of various synchronization technology,a realization of DTMB single carrier synchronization system algorithm flow scheme is proposed.It Includes timing adjustment,frame head mode detection and coarse frame head position estimation,coarse frequency offset estimation and deviation correction,variable step frequency sweep and deviation correction,thin frame head position estimation,sampling synchronization,fine frequency offset estimation and deviation correction.With the help of MATLAB software,the synchronization process has been carried out on simulation and analysis.And the result validates the synchronization process,which can well realize synchronization.Then,considering the performance of system and the difficulty of implementation,in view of the frame head position estimation of FPGA implementation,an improved frame head coarse estimates algorithm is proposed.The algorithm only take the real part of relevant accumulation,and the simulation results show that the improved algorithm is able to correctly estimate the coarse position of the frame head,and reduce the use of multiplier resources.In view of the existing sweep frequency algorithm with too many sweep number,an improved variable step sweep algorithm is proposed.By selecting the appropriate frequency point in the sweep stage,the result of the algorithm reduces the number of sweeping from 44 times to 20 times,attenuates the system complexity,the sweep estimate speed faster,but the estimated accuracy remains the same.Finally,using Altera's Stratix ? series' EP2S90F1020C4 chip as hardware development platform to implement and verify entire synchronization system.Test to get the hardware sequence chart of various modules.And the paper compares FPGA test results with MATLAB simulation results,which verify the feasibility of the various modules.