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Study On Digital Phase-locked Loop Motor Speed Control System Based On FPGA

Posted on:2014-09-21Degree:MasterType:Thesis
Country:ChinaCandidate:Z B WuFull Text:PDF
GTID:2268330422950680Subject:Control Science and Engineering
Abstract/Summary:PDF Full Text Request
Phase-locked loop technology in application to high precision motor speedcontrol has attracted more and more attentions in recent years. It has been foundthat there are three different realization in engineer application, they are softwarephase-locked loop method based on DSP, digital phase-locked loop method basedon FPGA and method based on dedicated chip. As method based on dedicatedchip is simple to use and does not require specialized knowledge of phase-lockedloop, it is the most widely used method. But there are still a lot of problemsabout it and its configuration is not flexible enough. Using FPGA to implementPLL control not only solve the problem of not flexible of using dedicated chips,but also is faster than the software method. Using FPGA can also reduce thecomplexity of the peripheral circuits, and improve anti-jamming capability. Thispaper is mainly focused on the research of all-digital phase-locked loop motorcontrol system based on FPGA, and proposes a new all-digital phase-locked loopmotor control solutions.First, we study the basic structure and working principle of phase-lockedloop in details. Then we introduced the applications of phase-locked loop inmotor speed congtrol, and analyzed some issues and technical problems of thephase-locked loop motor control system.Second, a new control scheme is proposed in this paper to meet our specialrequirement. In accordance with the scheme, we designed hardware and software.The hardware includes FPGA+DSP control board and the motor H-bridge driverboard. The software is the FPGA program modules, including the improvedphase frequency detector, FIR loop filter, adaptive PI controller and PWMgenerator.Moreover, the mathematical model of the motor, the driver and the FPGAmodules is illustrated. The parameter of the designed controller is optimizedaccording to the proposed mathematic model. The saturation and quantizationeffect is also analyzed. The response acceleration boost of the adaptive controlleris analyzed too.Finally, Some engineer experiment has been carried out to show theeffectiveness of our proposed methods, verified the functions of the improvedPFD, FIR filter, adaptive PI controller and PWM generator designed, and testedthe control performance of the system in different input signals.
Keywords/Search Tags:FPGA, PLL, motor speed control, PWM, adaptive control
PDF Full Text Request
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