Floorplan And Power/Ground Network Co-design Technique

As the VLSI manufacturing technology runs into the deep sub-micron stage, the decreasingVLSI layout feature sizes lead to the increased interconnect resistance, the increasing number oftransistors per area leads to the increased the supply current density, and higher clock frequencyleads to more significant inductance effect: All above factors make the IR drop (voltage drop) ofpower/ground network become larger. On the other hand, the threshold voltage of transistor scalesnonlinearly makes transistor more susceptible to the influence of IR drop, excessive IR drop willweaken the driving capability of logic gates, reducing circuit performance and lower noise margin.Moreover, the entire circuit may failure. Therefore, the IR drop problem should be paid moreattention to and be solved effectively in the early physical design cycle during the process of VLSIdesign. The traditional SoC design process deals with the IR-drop problem at the postlayout stagewhen the entire chip design is completed, and the process must return to the floorplanning stage tomake a new floorplanning if it violates voltage drop constraint. In the dissertation, according toSoC design flow and the characteristics of the IR drop, the floorplanning and power/groundnetwork design research for SoC is studied We propose an effective heuristic method calledfloorplanning and power/ground network co-design technique to reduce the IR drop. The methodmakes static voltage drop analysis step integrate into the floorplanning stage more quickly andefficiently. By testing MCNC benchmark circuits, the experimental results show that the methodcan fix IR drop problem effectively. The dissertation is mainly composed of the following threesections:1. Floorplanning has a great impact on the current density distribution of power/groundnetwork, since the performance of simulated annealing algorithm based floorplanning is limited, anovel slicing floorplanning algorithm based on fast simulated annealing has been proposed toimprove the efficiency and effectiveness of floorplanning algorithm.2. The topology structure of power/ground network has a great impact on the IR drop of thepower/ground network. In order to solve the convergence failure problem of traditional methodswhich increase line width or pitch to reduce the IR drop separately, a method increasing line widthand pitch simultaneously is proposed to reduce IR drop effectively. 3. Since the traditional SoC design process to reduce the IR drop is complex and inefficient, afloorplanning and power/ground network co-design method is proposed to optimize chip area andIR drop simultaneously and rapidly. Experimental results show that this method can fix IR dropeffectively.