Floorplanning For Multi-Voltage System-on-Chips

Low power is one of the most crucial challenges in the Nano era of IC design. Multiple Supply Voltage, MSV,can reduce the chip power of CMOS circuits most effectively nowadays.. So far the application of MSV in SOC design is in the form of voltage island designed by hand. MSV has brought great challenges to circuit physical design, especially floorplanning. Floorplanning with multi-voltage needs to consider voltage island generation, voltage level assignment, level shifter placement, voltage integrity of power grids and chip area and wire length and so on. This paper has generally studied the problem formulation and technical details of floorplanning with voltage islands. By proposing a series of floorplan strategies with voltage islands generation, we have made the following contributions:Floorplanning with Irregular Shaped Voltage Island (ISVI). In multi-voltage floorplanning, MSV is often performed in the form of Rectangular Voltage Island (RVI). Irregular Shaped Voltage Islands can achieve much better power savings in multiple supply voltage (MSV) technology. This paper proposes a simulated annealing (SA) based floorplanning method with ISVI generation using a Hazard and Heal strategy, in which the floorplan is represented by Sequence Pair (SP). In each perturbation of SA. a randomly chosen block is removed from floorplan and then inserted back to a proper position, to join certain voltage island. The solution space for every iteration is O(n2kvi), where n is block number and kvi is voltage island number. Every position with voltage island assignment is evaluated by a linear combination of chip area, wire length, power and voltage island cost. To avoid timing-consuming evaluation of O(n2kvi) possibilities, we define the conception of disruptor based on SP model and propose a fast Hazard method to construct ISVI by skipping lots of distant voltage island candidates while occasionally accepting seldom-emerged illegal (non-contiguous) candidates. To resolve the seldom-emerged non-contiguous voltage islands, a detailed Heal method is applied in each temperature. Experimental results show the proposed method is effective and efficient compared with the latest works.Floorplanning with Rectangular Voltage Island (RVI). Nowadays in the EDAtools, voltage islands are in the form of RVI and designed by hand. This paper improves the simulated annealing with insertion alter remove of blocks for floorplanning with MSV. To counteract the greedy insertion after remove (IAR) for blocks, this paper proposes the perturbation method of IAR of RVI:and voltage islands destruet the uniform global power grids. This paper studies the influence of voltage island positions on the power efficiency of the power grids and proposes a method to optimize the power grid integrity. Experimental results show that the proposed method reduces the number of voltage violation points while keeping wire length, chip area and power optimized.This paper systematically analyzes the competition and cooperation relationships between different optimizing objectives of floorlanning with voltage islands according to the above studies and experiments and generalizes the problem formulation of floorplanning with voltage islands. The methods mentioned in this paper can be applied in EDA tools or integrated with nowadays tools to improve chip quality and reduce design iterations.