Floorplan-Based Power Distribution Network Design And Optimization For SoC

As the process technology enters the deep sub-micron design era, chip designtrends to the SoC design. The reduced power supply voltage, increased power densityand thinner wires used make the power distribution network more important in thechip design. Thus, the design and optimization of the power distribution networkbecame a valuable research topic. However, it is a difficult and time-consuming workto modify the power distribution network after placement phase. Therefore, in order toenable the so called "single-pass design methodology", it is necessary to start solvingeletromigration and voltage drop problems at the early stage. Comparing with otherapproaches, our method proposed in this thesis is aimed at a fast and systematicalgorithm to design the initial power distribution network for SoC designs. We tookthe power consumption of the macros into account and proposed a more accuratemodel to simulate the reusable blocks. Then, the initial network was optimized to savethe routing resource by linear programming method. Experimental data shows that theproposed approach can construct robust power distribution networks with fewerrouting areas.The proposed algorithm has been implemented in a C program and can beintegrated with commercially available tools in existing SoC design flow.