The Soc Floorplanning Algorithm

The physical design of SoC under DSM is confronted with more challenges than before, such as stability, function, power, yield and the cost, etc. It will take long time to achieve design closure for the traditional flow and therefore, new design flow is explored to encounter so many difficulties. As the fisrt step, floorplan plays an important role in the physical design. The constraints could be integrated into a floorplan to reduce the RC delay, lower the congestion, improve timing closure and speed up the design process, which is significant to the design closure.Based on the study of several kinds of representations, the dissertation has research on the traditional floorplan, the floorplan with new constraints and relevant PG routing. In the study of traditional floorplan, an accelerated SA algorithm is included. Following presents the algorithm with SoC and IR-drop consideration, which focus on the floorplan with new constraints. And finally, a fast analytical model for power network is presented and an irregular network is constructed on this model.The accelerated SA algorithm takes the advantage of simulation annealing in floorplan to design new neighborhood solution for accelerating the convergence rate. Compared to the traditional floorplan, it speeds up the simulation annealing process, saves 30% above runtime and so gets better efficiency.The floorplan with SoC constraint leads the module perturbation in B*-tree by deflection P, which makes changes between two allowable floorplans through several perbutations to satisfy SoC constraint. Experimental results demonstrate the efficiency of the algorithm, whose additional core unilization is reduced above 1.6%.The floorplan with IR-drop consideration is based on the analysis of compact physical IR-drop model and the IR budget of every module. The proposed algorithm integrates the IR-drop constraint into the cost as well as the SoC constraint into the perturbation, which implement a SoC floorplan with low IR-drop.Finally, the Floorplan and Power Distribution Network Co-Design proposes a technique for fast estimation of the power supply capacity and a current path-based model is constructed for the analysis of the generated mesh. Compare to the traditional method, the complexity could be greatly reduced and the computational time is saved. Based on the proposed model, an irregular power network is constructed after applying topology optimization.