Design Of 8K×8 Asynchronous SRAM In 018?m CMOS Process

Since the development of integrated circuits,system-on-chip(SoC)has gradually become one of the main methods of chip design because of its many advantages.Memory is an indispensable part of it,and its performance has attracted more and more attention.Asynchronous SRAM Memory has become one of the current research directions of memory because of its unique advantages.This text adopts SMIC180nm craft to carry on the fully customized design to the asynchronous SRAM memory with the capacity of 64Kb.This paper first analyzes and designs the overall structure of the large-capacity asynchronous SRAM memory,and then designs the read and write timing of the memory in detail for its read and write operations that are completely asynchronous.Then in order to improve the reliability of the memory,double interlocking DICE memory cells are used to form a memory array.Then continue to analyze and design each peripheral circuit and verify the function through simulation.Which focuses on the analysis and simulation of the structure and performance of the sensitive amplifier and the address conversion monitoring circuit.The asynchronous SRAM memory in this design can correctly realize the read and write function.Last but not least,the layout of the memory is fully customized,and a protective ring is added to the layout to achieve the effect of reinforcement.The layout area of the memory is 3630847.1?m~2.After all the layout design work is completed,use the layout design rules of the process library to check.After the check results are passed,the layout netlist of the memory is extracted for post-simulation under different process corners.The post simulation result shows that the asynchronous SRAM can complete read and write operations correctly,the fastest read and write cycle can reach 6.8ns,and the power dissipation is 19.1m W.