The Implementation Of A High Performance Vector Processor

In order to meet the needs of processing of multimedia applications,the mainstream processor manufacturers have increased their corresponding extended architecture,for improving the performance of the media.And provides the instruction set with single instruction multiple data characteristics,referred to as SIMD instruction set.Altivec technology is a general purpose processor in the PowerPC architecture,which is based on the extended PowerPC instruction set,which is supported by the multimedia processing technology.In this paper,a vector co-processor,which is closely coupled to the main processor,is proposed.The design and implementation of the Altivec top level control path and the design and implementation of a simple fixed-point functional unit,which is one of the four functional units of vector co-processor are studied.The hardware and software verification scheme based on SystemVerilog verification platform is presented.The whole verificatio n scheme has the advantages of high completeness,reusability,reliability,efficiency and speed.In the area,the method of hardware reuse is adopted to reduce the area of the simple fixed point function unit.The results show that the hardware area of simple fixed point functional unit designed by the method of hardware reuse is reduced by 53% compared with the design without hardware reuse.In speed,the dynamic scheduling method based on the random access of the instruction queue and the distributed reservation station logic is handled.The instruction which all operands are ready is launched to the reservation station,and ease the impact of the processor performance.The experimental results show that the use of the dynamic scheduling algorithm for the implementation of the code can be reduced by 25.93%-20.47%,and the time of the execution of the fixed-point class instruction can be reduced by 13.42%-5.65%.