The Design And Verification Of Multiply Unit Of 600MHz YHFT-DX

YHFT-DX is a32-bit fixed-point high performance DSP based on VLIW architecture. In YHFT-DX, there are two Multiply Units and both are pipelined, which make YHFT-DX has high multiplication performance. It's a challenge to achieve the design goal of 600MHz for the Multiply Unit because of the numbers and abundant types of instructions, which made the internal structure complex.According to the design requirements of the YHFT-DX chip, this paper analyzes the critical factors which affects the timing and area from system level, module level and circuit level, and then implements Multiply Unit based on the mixed methodology. of Full Custom and Semi-custom. Finally the frequency of Multiplier Unit achieved 600MHz. The main contributions are as follows:1. Analyzing the function and pipeline of Multiply Unit, and three pipelines are adjusted and optimized by logic merging of different stage, the same treatment, logical move forward techniques and sharing registers.2. Implementing the design of critical modules based Full Custom methodology and optimizing the design with structural level, circuit level and layout level. In the design process, hierarchical sub-stations, reducing median operation,logical partitioning, reorganization or conversion technology to optimize the structure of key modules. In the circuit design besides uses the commonly used circuit structure, in addition designs a high driving capability register , reduces the logical progression. The layout of critical module are implemented and optimized, several layout methods such as slice-bit, source-drain share or route channel multiplexing and so on were introduced to reduces the long-line interconnection and the parasitic parameters. The above three level's optimization had guaranteed all custom-made module succession to satisfy the design requirements.3. Implementing logic synthesis and physical design.Completes Multiply Unit's floorplan, powerplan and the clock design according to the entire chip, and introduced the"useful skew"in the clock design to be balanced the internal timing for violation path.The design uses 130nm CMOS process, and the total area is 400×430μm~2. The verification result indicated that delay of critical path is 1.31ns. Compared with the result of ASIC, the delay of the longest path reduced about 37.5%, received a very large improvement in performance.