Design And Implemtation Of BP Component And Shuffle Unit In YHFT-Matrix Processor

DSP is designed specifically for digital signal processing, has been widely used in wirelesscommunication systems and other areas of social life. The research of DSP with our ownintellectual property rights not only has enormous economic benefits, but also is able to build asecure communications infrastructure to provide the basic protection.YHFT-Matrix DSP is a high-performance32-bit floating point DSP, uses VLIWtechnology and once emits10instructions. It is research and developed independently byNational University of Defense Technology. This paper design and implement the BP (bitprocessing) and shuffle units of YHFT-Matrix DSP processor based on an in-depth study of thecurrent processors architectures and instruction sets.BP unit is one of the three processing units in YHFT-Matrix DSP, and mainly performsshift instructions, bit-process instructions and pack/unpack instructions. The BP unit uses SIMDtechnology and can fully develop data-level parallelism of programs. The shuffle unit isimplementing the exchange of data among VPEs in vector processing unit. It has an independentSRAM for storing the shuffle mode to improving the efficiency of the implementation of the unit,so when the applications can be executed without occupying the system s key resources such asthe register file or memory bandwidth.In this paper, we verified BP and shuffle units in various stages such as the RTL simulation,the simulation after synthesize and the simulation after layout, that ensured the correction of thedesign. The experiment results show: the shuffle unit improves application performance by14.3%to27.6%, while the additional area overhead is only0.6%.We synthesized BP and shuffle units with using Synopsys DC (Design Compiler) underTSMC65nm process technology. The area of BP unit is581,856um2, which is accounting for3.7%of the total area of YHFT-Matrix, and the critical path delay is0.8ns; the area of shuffle unit is35,2326um2, accounting for only2.2%of the total area, the critical path delay is1.59ns. Both BPand shuffle units can meet of the target frequency requirement (500MHz) of YHFT-Matrix DSP.