Research On Automatic Generation And Simulation Method Of Asynchronous Networks-on-Chip

With the rapid development of semiconductor integration technology, the feature sizes of the transistors shrink rapidly, more and more circuits of complex functions were integrated on single silicon. The circuit techniques faced a series of problems, such as clock skew caused by the global, clock jitter, clock power consumption and design complexity. In recent years, globally asynchronous locally synchronous based on systems on-chip become a hot topic, considered as a new design approach. Asynchronous Network-on-Chip become the mainstream asynchronous chip interconnects architecture for next-generation chip systems because of its scalability, high modularity, high concurrency, clock localization and other advantages. In this paper, the asynchronous Network-on-Chip was considered as our target and the asynchronous chip network of key issues (network topology, synchronous/asynchronous interfaces, quality of service, routing algorithms, and design automation, etc.) were analyzed in detail. The asynchronous NoC automatic generation method were researched in detail and explored in-depth.First, the advantages were analyzed about the asynchronous NoC relative to conventional synchronous, and the knowledge of asynchronous design was introduced in this paper. Then, we start the research asynchronous NoC from on-chip network topology, exchange, routing algorithms, etc. and put forward a large number of advantages which does not have in synchronous NoC finally. A NoC design process based on IP library was proposed, on the basis of several NoC design process were analyzed and explored. It was designed by using communications and computing separation, combined with IP reuse technology, making between functional modules independent of each other. The automatic generation method for application-specifie network-on-chip was researched on the basis of IP library design process. The method uses conventional2D Mesh topology as a research platform, a network-on-chip was generated automatically from the application of the input, mapping, route assignment, automatic generation of four steps. Finally, We focus on particle swarm optimization (particle swarm optimization, PSO) and Genetic Algorithm (genetic algorithm, GA) hybrid optimization mapping and allocation strategies to achieve the shortest path based on load balancing algorithm, as much as possible to reduce the power consumption and bandwidth needs, take into account the load balancing link at the same time.In this paper, a simulation method for NoC was proposed based on the NS2. It used to assess topology, switching and routing algorithms, and design parameters such as the type of communication mode, and the communication load which have an impact on the average delay and throughput performance NoC architecture. It provides a scientific way to evaluate the performance of automatically generated network-on-chip. Comparative experimental results, the network-on-chip based on automatically generate method was proposed in this paper which have excellent performance in the link bandwidth, power and link load balancing,meeting the design requirements at the same time.