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Research On Low-power Design Methodology For Network On Chip

Posted on:2016-01-28Degree:DoctorType:Dissertation
Country:ChinaCandidate:F ZhouFull Text:PDF
GTID:1108330503475936Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
Reusable, extensible, and supportive of concurrent communication, Network on Chip(NoC) has become an effective solution to overcoming the problems of global interconnection and communication in complex SoC design. Given the large scale of SoC system based on NoC communication architecture, the power consumption is often considered the most important design constraint in the semiconductor devices technology of nanoscale. The increase of power in the system will result in the issues of the heat dissipation and the reliability of the chip. Therefore, the research of low power technology for NoC has important theoretical and practical significance. In this thesis, we study on the key technology of No C low-power design from the perspective of system-level and architecture-level, with main focus on the allocation of virtual channel and buffer resources in NoC router, the partition of the NoC voltage-island and the routing path allocation based on the voltage-island. Our work will guide the research on low power design methodology for NoC.The thesis firstly proposes a power-aware virtual channels allocation approach called SAVCA to reduce the area and power consumption caused by the average allocation of virtual channel resources in NoC. Based on the mathematical communication model for 2D mesh NoC, the average packet latency is calculated and used as constraint. The virtual channels are allocated reasonably, and SAVCA can reduce the number of virtual channels by improving the utilization rate of them. The effectiveness of SAVCA algorithm is verified by the multiple sets simulation experiments under uniform traffic flow and hot spot traffic flow. Experiment results show that SAVCA algorithm can reduce the number of virtual channels, and lessen power consumption by 29.9% maximum.Aiming to find solution for low utilization and long transmission delay caused by average allocation of buffer resources in NoC routing node, we study on the non-average allocation scheme of buffer resources, and propose two different buffer resource allocation algorithms: performance-?rst algorithm called MP and performance-constrained algorithm called SP. MP uses multi-path transmission mode to ?nd the optimal tra?c-load distribution, achieves the best performance of the transmission delay, and needs the minimal buffer budget. SP uses single-path transmission mode. The performance of transmission delay is used as constraint. We formulate buffer allocation as an optimization problem for the two algorithms based on the queuing theory, and use the simulated annealing algorithm to allocate the buffer resources. These two algorithms are verified by multiple sets simulation experiments under uniform traffic flow and hot spot traffic flow. Experimental results show that the proposed algorithms can signi?cantly reduce total buffer usage and guarantee performance requirements.To solve the problems of system reliability, transmission delay, and energy consumption caused by the partition of No C voltage-island, as well as increased complexity of the system due to excessive number of voltage islands, we propose a VFIs partition method called ILPVIP for NoC based on ILP algorithm. ILPVIP can optimize energy consumption in the NoC system while ensuring performance(delay and reliability, etc.). The validity of ILPVIP has been verified through E3 S tests, various random benchmarks and a multimedia system MMS. Simulation results show that ILPVIP can reduce the total energy consumption of the system by 33.6% at most while satisfying multiple constraints.Finally, the thesis studies on communication path allocation based on NoC voltage-island, which would lead to transmission delay, communication energy, and network congestion. We define the link-balance model, and present a genetic algorithm based routing approach called GAR. GAR generates a deterministic deadlock-free minimal routing path for each communication trace of given application, so as to minimize total communication energy consumption and balance the traffic across the links under bandwidth constraint. Evaluation performed on E3 S, various random benchmarks and a multimedia system MMS confirms the efficiency of the proposed approach. Experimental results show that GAR can cut energy consumption by 21.7% and link bandwidth requirement by 21.8% on average compared to the GLR algorithm and the GAR algorithm.
Keywords/Search Tags:Network on Chip, low power, virtual channel allocation, buffer allocation, voltage islands partition, path allocation, routing scheme
PDF Full Text Request
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