| Nearly a decade, depending on the rapid development of semiconductor process technology, EDA (Electronic Design Automation) technology and VLSI (Very Large Scale Integration) technology are propagating very quickly. That one or multiple CPU units and features will be integrated on a single chip has been not a dream, we call this single integrated chip as SOC (System On Chip).The general development process of SOC:users define the entire system by HDL (Hardware Description Language), and then it will be verified by simulation tools for simulation. After the simulation, the designer will send the design layout or source code to manufacturers of semiconductor chip to tape out. However, Moore’s Law, the complexity of the verification is proportional to the square of the chip area, the chip capacity of unit area is doubling every18months, the complexity of verification is doubling every6-9months too. In order to solve the difficulties of SOC verification process, we have to further optimize the programing, therefore, shardware and software co-verification is the primary means of SOC verification, Based on this technology, the software module running on a high speed hardware device will be more time-saving, For example, the simulation of Is timing behavior is likely to be5-6hours in software environment, But the same Is has no different with real Is on the FPGA, the gap is obvious.The main content of this paper is to introduce the automation solutions of system integration, code migration, the setting of environment and other structures in the process of RSP verification, I will combine the content of the article in the actual design of the ICT projects, Finding a specific case as evidence, to explain the difficulties and details of the verification process. |
