Verification Methodology And Implementation For GPS/COMPASS Ⅱ Dual-mode Baseband Chip Using Vera

With the competition in satellite navigation business between countrise, the current satellite navigation systems are transforming from the solo GPS to multi GNSS constellations. Chinese own satellite navigation system, "COMPASS" also joined in them betimes, and has occupied a more and more important status due to the construction of COMPASSⅡ. Meanwhile, the multi-constellation satellite navigation has started to grow into a new technology, and the navigation terminal which supports multi-navigation system will become the mainstream product in the future. The baseband chip of multi-constellation, as the core component of the navigation terminal, is becoming the object of the navigation manufacturers. On the other hand, with the constant increasing technology level, integration and speed, the design of SoC chip becomes more complex, making the chip verification increasing important and difficult. The research subject in this paper is the function verification of GPS/COMPASSⅡdual-mode baseband chip.Based on SoC verification technology, the paper promote a comprehensive and feasible verification plan for the functional verification of GPS/COMPASSⅡdual-mode baseband chip. Under the plan, we build a modular, layered and efficient testbench using Vera language and Reference Verification Methodology (RVM), write automation script, and design the appropriate testcases in order to implement both the module level and system level functional verification of GPS/COMPASSⅡdual-mode baseband chip. Besides, we use coverage-driven technology to improve the verification coverage, ensuring verification more completely.Verification result shows that, with the help of various testcases, the testbench we design in this paper can achieve the functional verification of GPS/COMPASSⅡdual-mode baseband chip successfully and the coverage has reached the desired goal. Additionally, each of the signal level, command layer, function layer, scene layer and test layer in this testbench has its own function modules, some of which can be used in other verification environment. Thus, this paper concludes with a IP core for verification(VIP) of baseband ship, committed to improve the efficiency of the relevant verification and shorten the chip development cycle.