The Design And Verification Of Compass Ⅱ RNSS Baseband Chip Interface

As the Compass navigation system constantly developing, the Compass satellite navigation system will be used in more different areas. Therefore it will have great benefits to the society and is generating great economic profit. This thesis is based on the project "The Design of Semiconductor Integrated Circuits for Compass II RNSS User Devices." As part of the project, my purpose for this thesis is to design a reliable interface module for the satellite communications and navigation chip. I focus on the design and verification of the three soft IP cores (Ⅰ~2C Interface, UART interface, and SPI interface). I also look into the design and verification methods of deep sub-micron chips.The Top-Down method is used for designing the chip and the Bottom-Up method is used for testing. According to the requirements of the Compass II user devices and the bus protocol specifications, firstly we design the architecture of the chip, and plan the development process. Secondly I use discrete logic and finite state machine methods with Verilog HDL language to program all soft IP core on RTL-level. Then I write the test platform and adopt ModelsimsE6.2b of MENTOR to simulate all soft IP cores to ensure that the basic function is correct. Finally I use the Quartus II EDA integrated development tool to program compiler, placement and routing, configure and downloading. In the CCS3.3 environment I implement interface service software to verify the three interfaces on an FPGA verification system. After software verification each IP core has been tested to run properly and achieve the design requirements. In this thesis, the research will accelerate the design of the chip, improve its reliability, and help promote the industrialization of satellite navigation and miniaturization of the user device. So this issue has important theoretical and practical significance.