A Study Of On-line Train Driving System Monitoring Device Based On DSPs And FPGA

Mechanical transmission system is the core of high speed train, real time monitoring of its status is very important for enhancing the safty and reliability of the train. Recent years, with the rapid development of railways, the demand of train on-line monitoring is becoming stronger and stronger. Meanwhile the continuous improvement of hardware technology also provides a good opportunity for the realization of train on-line monitoring.In this paper, the consist of the on-line train driving system monitoring device and its every part’s functions are given. The hardware design and embedded software development were finished mainly for the acquisition&process board, which is with the architecture of DSPs and FPGA, to realize the application of train driving system’s fault analysis.In this design, DSPs is in charge of on-line data processing while FPGA performs the control of peripheral devices. The floating point DSPs TMS320C6713and Cyclone Ⅲ FPGA EP3C16F256were chosen in order to meet requirements of the system. EMIF bus was used to transfer data while UART bus was used to transfer configure information between DSPs and FPGA. Then the digital and analog circuit of the board, including signal modulate circuit, minimized system circuit, store circuit and communication circuit etc, and the layout of PCB were completed. Finally, in the FPGA’s program development, customized IP core, the SOPC system based on Nios Ⅱ soft CPU and C language diver were developed to realize the embedded μC/OS-Ⅱ operation system. While in the DSPs’program development, a new second bootload and rapid Flash burn method were proposed, the communication with FPGA and primary fault diagnose algorithm were realized as well.As a result, the on-line train driving system monitoring set can achieve the performance requirements as designed, and the acquisition&process board realized the requirements of signal acquisition, on-line data processing, correct judement of the driving system’s status according to the recent fault diagnose algorithm and the function of communicating with other boards. At the same time, the design of the acquisition&process board based on the architecture of DSPs and FPGA is resonable and has mutual complementarity, its flexiable inter communication and the reconfigurability of SOPC system provides very convenient for the realization on the same hardware of the following new algorithm.