Research On Data Monitoring Technology Of VME Bus Based On FPGA

The VME bus is a general-purpose module backplane bus that is widely used in military,medical,transportation,and industrial control systems due to its high transmission rate,flexible transmission mode,compact structure and high reliability.As new aircraft being in service,the repair requirements for airborne VME modules will increase in the coming years.In order to systematically master the repair capabilities of VME bus aircraft boards,there is an urgent need to strengthen the technical reserves for research in this area.VME bus data monitoring technology will become an important technical research content.Based on the above background,in order to master the VME bus data monitoring technology,the paper takes Altera's Cyclone III series FPGA as the core,and carries out VME bus data monitoring technology research for the presence or absence of SCV64(VME bus protocol chip).The thesis mainly completed the following work:1.Based on the system analysis of VME bus architecture,function of each component,working mode of transmission cycle,etc.,in order to realize effective monitoring of VME bus data,the research ideas of developing VME bus slave module and VME bus monitoring module are proposed.The specific hardware design scheme and software development scheme of the VME bus slave module and the monitoring module are given.2.Based on the VME bus interface protocol chip SCV64,a slave module with a function of accepting VME bus read and write operations has been developed.Its hardware architecture and each parts of the circuit design are given,including minimum system of FPGA,interface circuit of SCV64,bus buffer circuit,level conversion circuit.Based on the Verilog HDL language,in the Quartus II 9.1environment the functional software of the slave module is developed and the timing simulation is performed.Problems that need to be paid attention to during hardware design and software development are given;3.Based on the NIOS II processor SOPC system,a bus monitoring module with the function of monitoring and collecting VME bus signals has been developed.The hardware architecture and various parts of the circuit design are given.The circuit specifically includes the minimum system of FPGA,the SDRAM circuit,the Flash circuit,the serial port level conversion circuit,and the bus buffer circuit.In the Quartus II 9.1 environment,SOPC systems and application software were developed.Problems that need to be paid attention to during hardware design and softwaredevelopment are given;4.The MVME3100 single board computer,VME bus chassis,industrial computer and the developed slave module and monitoring module are used to build the VME bus monitoring system test platform.With the cooperation of the MVME3100 single board computer,the developed module was tested and verified.The module's power-on initialization,register configuration,and the function of accepting VME master module data reading and writing are tested and verified.The UART transmission,signal acquisition,and overall function of the VME bus monitoring module are tested and verified.The test results show that its function is effective.Through this subject,not only can the VME bus communication mechanism be systematically grasped,but also provide technical support for the subsequent working state analysis and fault location diagnosis of the airborne VME bus module.