Research And Design Of Low Power100MHz8-bit Pipeline ADC

The thesis presents the design of a low power1.8V100MHz8-bit pipeline Analog-to-Digital Convert.Making full use of the holding time, this thesis designed the two-phase non-overlapping clock generator. The OTA uses the circuit of fully differential boosted telescopic cascode to get high gain and low power, as well as uses the design of common-mode feedback to avoid the power mismatch. The dynamic comparators which can keep the analog signal from pipeline stage stable during the high frequency sampling phase are lack of kickback noise.The highlights of this thesis is the low power design methodology. We use the dynamic comparators and the telescopic architecture amplifier to decrease the power, as well as a1.5bit/stage pipeline ADC with9stages which has the lowest power. the amplifier in each stage is scaled down gradually with appropriate factor.The thesis analyzes how the error of OTA (offset voltage and gain error) impact to the performance of a high-speed low-power ADC. WE verified the results of the analysis by using Matlab system modeling and determined the target of the OTA.The ADC which designed with GSMC0.18μm2P6M CMOS process works under1.8V power supply and the chip has been tape out. The consumed die area is1379umx838um, the power dissipation is96mW with low power design. This thesis mainly uses Synopsys Hspice and Cadence Spectre to simulate designed sub-circuits, module circuits and the whole pipelined ADC system, while use MATLAB to analyze the simulating results’static and dynamic performances. The results show that, under TT corner and400KSPS sinusoid input signal, ADC’s static performances include a DNL of±1.02LSB and an INL of±0.8LSB, dynamic performances include a SNR of49.0847dB, a SINAD of46.9221dB, a SFDR of51.2152dB, and the THD is-50.9868dB.