Research And Design Of Ultra-low Power Pipeline ADC

With the development of digital information processing technology, ADC (Analog to Digital Converter) has been widely used in the fields of wireless communication, data collection, etc. Additionally, with the popularity of portable devices in recent years, and consideration for the cost, market and environmental protection, ADC’s ultra-low power design has become a hot issue at present.To achieve ultra-low power consumption, an8bit pipeline ADC with only160μW average dynamic power consumption is designed in this paper. The ADC which designed with SMIC0.18μm1P6M CMOS process works under1.2V power supply and its typical sampling rate is500KSPS. In order to achieve the ultra low power design goals, this paper mainly adopts two methods. The one is setting the MOSFETs of operational amplifiers to work under subthreshold region to reduce the circuit branch current and the required supply voltage. The other one is improving and optimizing the circuits’structures. Based on the layout design principle and rules of consideration of mix signal IC, the full custom layout of8bit pipeline ADC is designed.The designed pipeline ADC has seven MDACs in total, and the MDAC’s structure is1.5bit per stage. This paper mainly uses of Synopsys Hspice to simulate designed sub-circuits, module circuits and the whole pipelined ADC system, while use MATLAB to analyze the simulating results’static and dynamic performances. Simulation and analysis results show that, under TT corner and500KSPS sampling rate, ADC’s static performances include a DNL of-0.34LSB～2.85LSB and an INL of-2.24LSB～1.91LSB, dynamic performances include a SNR of43.5dB, a SNDR of42.5dB, a SFDR of49.1dB, and the effective number of bits ENOB above6.78. The layout uses of Cadence Virtuoso to design, the core area is744.25×619.38μm2.