Simulation Research Of Gate Enhanced Power UMOSFET With Deep Trench Dielectrics Engineering

With the evolution of power industry and the improvement of environmental awarenessin recent years, high efficiency and energy saving are taken seriously more and more.Therefore, the requirement of the power consumption and power conversion efficiency of thepower MOS devices has been increased constantly. Power devices with the property of highblocking capability but lower on resistance are required in many applications of modernpower electronics. Power trench MOSFET (UMOSFET) is a power semiconductor devicewhich developed on the basis of VDMOS and VMOS. Power UMOSFET has been widelyused in many kinds of power management and switch because it has high integration, lowon-resistance, fast switching speed and low switching losses. A number of device conceptshave been proposed in order to improve tradeoff between specific on-state resistance (RSP)breakdown voltage (BV). The most noticeable are the introduction of the RESURF effect andthe superjunction (SJ) effect. In recent years, based on the depletion of the drift region byMOS capacitors, some equivalent discrete devices have emerged.The main contents of this thesis are about the breakdown voltage， the specificon-resistance and gate charge of Power trench MOSFET devices. Simulation research of gateenhanced power UMOSFET with deep trench dielectrics engineering. The split-gate powerUMOSFET with multiple trench dielectrics (MTDSG-UMOS)，a new way of approach toimprove the electric field distribution in the drift region, is proposed to improve RSPversusBV tradeoff and also can give a good RSPversus Qgtradeoff. MTDSG-UMOS bring forthenhanced breakdown voltage by helping to deplete the n-drift region horizontally. Thecontents of the research as follows:(1) The theoretical analyses research of gate enhanced power UMOSFET with deeptrench dielectrics engineering. Based on the analyses and disadvantage or advantage of OBand GOB, a new way of approach to improve the electric field distribution in the drift regionhas been provided. This work provides a theoretical analyses approach addressed to thisstructure. The dielectric layer of structure is composed of several dielectrics with different Kvalues，which replace the single dielectric before. By the multiple trench dielectrics modulatethe electric field profile in the drift region, a higher breakdown voltage for devices and a lower specific on-state resistance can be realized. Based on the analyses, design referencemodels have been proposed. So, geometrical and technological parameters can be easilyoptimized by means of simple expressions.(2) The structure and simulation of gate enhanced power UMOSFET with deep trenchdielectrics engineering. A novel split-gate power UMOSFET with multiple trench dielectrics(MTDSG) is proposed. The key feature is that the dielectric layer of MTDSG-UMOS isdivided into several layers, employing different K values dielectrics for each one. With threecommon dielectrics as an example, an analytical model is provided to demonstrate thesuperior electrical performance of this structure. The theoretical analyses were also carefullyvalidated through two-dimensional numerical simulations at voltage capability120V and180V for better understanding. Then the comparison of performance for MTDSG-UMOS andGE-UMOS has been studied to show the advantage over the conventional gradient oxidethickness structure. This device shows a15%reduction in the specific on-state resistance anda64%reduction in Qgat a breakdown voltage of123V, as compared with the GE-UMOSdevice. Numerical simulation results indicate that the proposed device features highperformance with an improved figure of merit of Qg×RSPand BV2/RSP. Moreover,MTDSG-UMOS is avoided the difficulties in forming a desired oxide slope of GE-UMOS.(3) Improve the structure of gate enhanced power UMOSFET with deep trench dielectricsengineering. A new structure of MTDSG-UMOS with low Gate-Drain Charge（Qgd）isresearched. This structure is proposed to decrease the Qgdof the device. By introducing ashielding polysilicon layer region on top of split polysilicon gate, the parasitic capacitor isreduced. The shielding polysilicon layer is part of split polysilicon gate and isolated from theupper gate electrode. From this investigation, it has been demonstrated that the structure pushQgdeven further to achieve a good RSPvs Qgdtrade off. This structure shows a70%reductionin the gate-drain charge and a61%reduction in the FOM of Qgd×RSP, as compared with theMTDSG-UMOS device. The low Qgdwill allow this structure to achieve a good efficiencyeven in high switching frequency converter.