The Research Of 100V Power Devices And Their Gate Charges

In low-voltage(<150V)and high-frequency applications,low charge between gate and drain can increase the switching speed of the device while meeting high power.Therefore,high power and high frequency become the development directions of the power semiconductor devices.High power devices require a high breakdown voltage(BV)while having a low specific on-resistance(Ron,sp).However,due to the 'silicon limit',the Ron,sp increases exponentially with the BV,limiting the development of high power devices.For the applications of the low voltage devices,the specific charge between gate and drain(QGD,sp)increases.This results in a decrease in the switching speed and limits the development of high-speed power devices.In this paper,by studying the model of breakdown voltage of the power device and the theory of the gate charge.The structure of the device is rationally designed,so that the device meets the requirements of high voltage,low specific on-resistance and gate charge at the same time.A new structure LDMOS with double trenches and trapezoidal gate(TGDT LDMOS)and a split gate LDMOS with double vertical field plates(SG DVFP LDMOS)are proposed.And the author also researches the numerical simulation and mechanism of the new structures through the simulation software,and design of the new structures of the process and production program of the layout.(1)A novel trapezoidal gate and double trenches(TGDT)LDMOS is proposed.One feature of the device is that two dielectric trenches which are equivalent to two field plates are introduced in the drift region.The two dielectric trenches not only modulate the body electric field to improve the breakdown voltage of the device,but also assist to deplete the drift region to reduce the specific on-resistance.Therefore,the new structure obtain the maximum power figure of merit(FOM1).According to the thick gate oxide technology of the gate charge reduction methods,a trapezoidal gate structure is used.Thereby the conduction loss of the device and charge between the gate and drain are reduced.Therefore,compared with the conventional trapezoidal gate TG LDMOS and trapezoidal gate single trench TGST LDMOS,the power figure of merit FOM1 of the TGDT LDMOS is increased by 108.8%and 56.6%,respectively.Compared with the rectangular gate double trenches RGDT LDMOS device,the charge between gate and train of the TGDT LDMOS is reduced by 42.5%and the FOM2 is reduced by 34.2%.(2)A novel split gate and double vertical field plates(SG DVFP)LDMOS is proposed.The first feature of the SG DVFP LDMOS is that the SG with gradient gate oxide is introduced.The SG reduces the charge between gate and drain(QGD)owing to the thick gate oxide.The second feature of the SG DVFP LDMOS is the presences of the DVFP and P-pillar.They modulate the distributions of the bulk electric field and assist to deplete the drift region.So the specific on-resistance is decreased and the BV is improved.The source VFP reduces the contact region between the gate and drain,thereby the QGD is reduced.Compared with the conventional SG LDMOS and RG DVFP LDMOS,the power figure of merit FOM1 of SG DVFP LDMOS is increased by 123.2%and 86.6%,and the loss figure of merit FOM2 is decreased 16.9%and 37.2%.(3)The process flows of the TGDT LDMOS and SG DVFP LDMOS are proposed in meeting the existing technological conditions.Finally,two layout designs of the new structures are performed according to the layout design rules.