The Characteristics Research Of Noval Power UMOSFET Devices

Power trench-gate MOSFET (UMOSFET) is a semiconductor device which developed on the basis of VDMOS and VMOS. Because the power UMOSFET can reduce the device on-state specific-resistance (RON) efficiently in process, and handle larger turn-on current, so it is developed in computers and other consumer electronics more rapidly in recent years. At present, the power UMOSFET technology is widely accepted in low-voltage MOSFET product markets, and with a high share. However, breakdown voltage (VBD) of power UMOSFET is still lower than that of lateral device. Today, therefore, the main research of power UMOSFET is to improve the VBD as much as possible on the base of less difficulty of manufacturing process, or to reduce the RON of device as much as possible in the allowed breakdown voltage area.The ideas of this thesis are applying the effects of the heterojunction generated by Si/SiGe and Si/SiGeC to improve the carrier mobility in the channel or drift region, and optimize the characteristics of power UMOSFET device. A novel technology, which is called Gate Enhanced UMOSFET (GE-UMOS) structure for the first time in this paper, the key of this structure is the polysilicon electrode is connected to the gate electrode. The Gate Enhanced with Split gate UMOSFET (SGE-UMOS) is proposed to modify the drawbacks of wasting silicon room and limiting parasitic capacitor about the gradient oxide-bypassed UMOSFET (GOB-UMOS).Several kinds of devices are designed as following:(1) Strain Si/SiGe, SiGeC power UMOSFET structure were presented and compared with conventional UMOSFET in IDS-VDS characteristics. The Si/SiGe and Si/SiGeC hetero-junctions could improve the carrier mobility and IDS with lower Vth and RON. Therefore, on the basis of meeting VBD requirement, the strain Si/SiGe and SiGeC channel UMOSFET had a greater improvement than conventional UMOSFET in RON, IDs-VDS and temperature characteristics.(2) The feasibility of applying the semi-superjunction (Semi-SJ) with SiGe-pillar (SGP) concept to power UMOSFET is studied in this paper. The electrical performances of SGP are compared with the conventional semi-superjunction (CSSJ) power MOSFET through 3D device simulation work in terms of RON, VBD, the effect to change the Ge mole fraction in the SGP and the thermal stabilization. The results show that the RON is reduced by 44% on the base of VBD reducing only 4.8%, tradeoff RON vs. VBD and thermal stabilization of SGP are superior to that of conventional Semi-SJ since the strain effect inducing into the SGP structure in the low power device application.(3) GE-UMOS is proposed to decrease the RON of the device. The key feature of this structure is that the deep trench polysilicon electrode is contacted to the gate electrode, maintaining the VBD and forming the high electron current density at side n-drift region, resulting in the lower RON compared to the superjunction (SJ) structure and gradient oxide bypassed (GOB) structure. But the parasitic capacitor increase a lot for the two electrodes connected together. So the Gate Enhanced with Split gate UMOSFET (SGE-UMOS) structure is proposed and simulated as compared to GOB-UMOS. The width of SGE-UMOS drift region w could be reduced, and increase the impurity concentration, so the RON of SGE-UMOS is lower than that of GE-UMOS, GOB-UMOS and SJ-UMOS. Because the oxide-bypassed polysilicon electrode is floating, the FOMs (Figure of Merit) are improved as compared to GOB-UMOS.