Design And Implementation Of H.264Decoding Algorithm Based On FPGA

H.264, which is proposed by the Joint Video Team of the ITU-T Video Coding Experts Group (VCEG) and ISO/IEC Moving Picture Experts Group (MPEG), is a highly compressed digital video codec standard. By this standard, in the same image quality, the compression efficiency of H.264is2times than MPEG2’s and1.5to2times than MPEG-4’s. It not only retains the advantages of conventional compression technology but also has many other advantages that other compression techniques lack, such as low bit rate, fault-tolerant, high-quality images, and network adaptability. Therefore, H.264is considered the most influential industry standards.H.264decoder is divided into five main steps, namely Stream Processing, Inverse Quantization Inverse Transform, Prediction Decoding, the Context Adaptive Variable Length Code and Deblocking Filter. Since huge amount of data would be processed during H.264decoding, the soft decoding will consume a lot of resources with low speed, a dedicated hardware-based decoder chip technology becomes popular.In this thesis, a FPGA (Field Programmable Gate Array) based hardware platform solution is proposed for the problem of real-time H.264decoding. A pipelined segmentation technique is used to improve the system frequency; according to the statistical properties of the signal, gating off idle modules are used to reduce system power consumption, while reducing a certain amount of computation according to the characteristics. In the bitstream parser, a128-bit dual-port ring buffer is designed dedicated to the communication between the original video memory and the mixing-length decoder. When64bits of the stored data is read by the mixing-length decoder, the ROM storing the original video is read immediately for providing a steady stream of video data; for the first "1" detector, the16-bit input data is divided into3sub detectors with unequal priority according to statistics, each sub-detectors can be individually turned on or off, the sub-detectors with high probability is activated first, other detectors activated only when higher priority detector fails or turned off, in order to reduce system power consumption. For CAVLC decoding, a4-way parallel technique is used to increase the processing speed.The experimental results proved that the basic functions of H.264decoding algorithm is implemented in this thesis. When the system clock is110MHz, the decoder can decode176×144pixels H.264Baseline level video well. The design implemented the H.264decoding algorithm, which is an effective solution for real-time problem.