Design Of H.264 Video Decoder Based On FPGA

H.264 is joint development of the video compression standards by the ITU-T Video Coding Expert Group (VCEG) and ISO/IEC Moving Pictures Expert Group (MPEG). Using the latest video encoding technologies such as the entropy coding based on the context, intra prediction, 4×4 integer conversion, 1/4 pixel accuracy motion estimation , etc., H.264 has the merits of a high compression ratio, high image quality, good network compatibility and so on. It has a widespread application in digital television broadcast, real-time video communication, network streaming multimedia and other various aspects.In depth study of the H.264 video compression standards and considering of the charactics of Nios II and FPGA, the paper proposes a low-cost H.264 video decoder based on embedded systems of SOPC. The paper also accomplishes the FPGA module design of entropy decoding, inverse quantization, inverse transformation and intra prediction.The paper includes the following content:1. The paper deeply studies the H.264 video compression standards and proposes a H.264 video decoder system based on embedded systems of SOPC.2. In depth study of the principles of entropy decoding, inverse quantization, inverse transformation and intra prediction, the paper accomplishes their algorithm design and discusses FPGA modules design in detail.3. The paper carries out two optimized methods of CAVLC table's looking up: One is Classifing the code table according to the count of zeros before the first"1", which realizes the table look-up algorithm improvement. The other is replacing the table look-up way with the arithmetic operation to realizing the decoding according to the strong relationship between the symbols in the same table. The comprehensive simulation indicates that the improvements cost less resources but improve the decoding speed.4. In the designing of inverse transformation and inverse quantization module, the paper uses the same module according to their similar operation character. Two-dimensional transformation is accomplished by twice one-dimensional transformation which is carried out by fast butterfly-shaped operation. The inverse quantification is accomplished by FPGA interior hardware multiplier for improving the processing speed.5. Through analyzing the algorithms of calculating predicted values in the intra prediction, the predicted value in most of prediction modes is calculated by a general arithmetic circuit which sums first and shifts again, and is processed in parallel through 4 arithmetical units for improving the processing speed.The result showed that it's practicable of the H.264 video decoder based on SOPC proposed by this paper. For CIF it can satisfy real-time decoding requirements of 25f/s, which has unique advantage and good space for development in speed, cost, power consumption, scalability, and so on.