Study On H.264/AVC Based Video Coding Technique And Its FPGA Realization

H.264/AVC is the newest video coding standard, which is developed by ITU-T and ISO. Compared to H.263 and MPEG-4 Simple Profile, The compression performance of H.264 is improved significiantly. In the same reconstruction quality, H.264 can reduce almost 50% bits stream compared to H.263. Further more, H.264 also has better adaptability of IP and ridio channel, which hae been widely applied in video communication field, digital broadcasting video and video storage&play back field.Compared to traditional video compression standard, H.264 impreoves mainly on prediction metholds, Integer transform&quantization and entropy coding metholds. H.264 improves its performance in cost of its codec complexity, which makes it's much more difficult in real-time video applications. Hence, Using FPGA to realize some complex algorithms has been treated as the research hotspot in video compression field. According to the actual hardware experimental platform, a simple but practicable coding system is designed, which based on the deep study on the principle of H.264/AVC and the analysis of complexity of its hardware realization.The Intra prediction technique is discussed detailly. And Matlab simulation is employed to demonstrate all kinds of intra prediction mode in both luminance and chrominance. A simple but practicable sum and arithmetic shift operation is proposed to realize and construct the whole intra prediction operation, which extremely reduce the realization complexity of the prediction circuit. Meanwhile, a multi-mode searching in parallel methold is also proposed to select the priorit prediction mode, which can make full use of the hardware's parallel processing ability.The principle of integer DCT transformation, residual levels quantization, the Hadamard transformation of chroma DC levels and their reverse process are expatiated in detail. To avoid the complex matrix computation, a rapid butterfly operation based integer transformation is proposed to significantly reduce the complexity of hardware realization.The principle of CAVLC is discussed in detail. Some important coding arguments are analyzed with statistical methold. Further more, a multi-clock domain processing and pipeline technique are proposed to significiantly improve the throughput of the encoding circuit. Besides, arthimatic operation is also used to replace some regular look-up tables to save hardware memory resources. Finaly, Altera CycloneII serial FPGA device is adopted to verify some key function units in the designed H.264 codeing system.The feasibility and validity of the coding system are also verified by analyzing the experimental results.