MCU Low-Power Design Technology And Its Power Analysis

In the last few years, the scale of VLSI has increased tremendously with the sharp advance of integrated circuit fabrication technology which leads to ever-growing chip power dissipation. When feature size is coming into the DSM (Deep Sub-Micron) era, power dissipation has become another design metric which has important effects on VLSI besides timing and area. And nowadays, low-power design technology has given rise to low-cost and high-reliability ICs. There are three major sources of power dissipation in a CMOS circuit, they are switching power, short-circuit power and leakage power. Among the above three types of power dissipation, switching power due to capacitor charge/discharge is predominant. Thus reducing circuit switching power can achieve optimal overall result which needs combined optimization of supply voltage, capacitive load and switching activity.This thesis first provides a broad insight into the essence of low-power design technology and makes emphasis on switching power reduction techniques. To reduce switching power, designing certain type of low-power flip-flop is the foundamental way. Then seeing this, the author proposes a new low-power pulse-triggered flip-flop by careful consideration. This flip-flop has a low clock load, eliminated internal node redundant switching activity and a high speed due to its semi-dynamic structure. Experiment results show that it has the advantages of low-power and high-speed.After successful implementation of this low-power flip-flop, it is applied to a Freescale MCU. Mixed-signal simulation results prove that a notable reduction in chip power dissipation has been achieved compared with the original design using master-slave flip-flops. Then power effects on chip power grid are found and optimization on power grid is fulfilled.