Design Of A DSIO Module For IC Tester

Integrated circuit testing technology has evolved with the development of integrated circuit technology,and can be seen in the research and development,design,production and application of integrated circuits.In recent decades,with the development of very large scale IC manufacturing technology,a certain number of digital pin IC are widely used,such IC testing requires IC testers to be able to perform hundreds of voltage,current and timing tests,as well as millions of functional tests,which means that a large number of test vectors need to be stored and sent to the device under test.Therefore,how to facilitate the functional testing of IC with these characteristics has become an urgent problem.This paper begins with an introduction to the test vectors involved in the structural and functional testing of digital IC testers.An IC tester test vector storage management module(DSIO,Digital Signal Input/Output)is designed based on the test requirements,and the module design principle,functional description and the solution of the main existing problems are presented.According to the general composition of the digital integrated circuit tester,the module hardware in this paper mainly consists of FPGA(Field Programmable Gate Array)control processing core and DDR3 SDRAM(Double Data Rate 3 Synchronous Dynamic Random Access Memory)storage media.The module specifically implements the following three parts of functionality: Pre-read processing section,to reduce the test vector readout path latency and complete the pre-test test vector processing from DDR3 SDRAM to the FPGA internal block memory;DDR3 SDRAM storage control section,this section completes the test vector storage management of DDR3 SDRAM multi-port read and write control,because this paper classifies the test vector storage management by different ports,and DDR3 SDRAM has only one set of data and address control bus,so this section completes the different ports to DDR3 SDRAM read and write access control design,to solve the multi-port cache at the same time to a single DDR3 SDRAM read and write data requirements;The read/write request arbitration section delineates the read/write priority of different ports to DDR3 SDRAM according to the actual application requirements,arbitrates the request of each port according to the priority,and sends an answer signal to distribute DDR3 SDRAM memory address and data bus control.Finally,the control function module involved in the above-mentioned DSIO module of the digital IC tester is implemented in hardware on the digital channel board of the IC tester equipped with FPGA and DDR3 SDRAM,and various tests are performed.Through the digital channel board on the DSIO module performance testing,the test results show the correctness of the design scheme in this paper,the module function to meet the design of the expected requirements.