A testing methodology and test chip design strategy for IC fabrication process assessment, problem diagnosis, and yield analysis

Very large scale integrated circuit (VLSIC) chips contain over a million transistors. With continued innovation in IC fabrication technology, it is predicted that IC chips will contain up to one billion transistors by the year 2000. The realization of these ultra-large scale integrated circuit (ULSIC) chips depends on the continued reduction in IC chip defect densities.;A new methodology and the appropriate electrical test structures, test software, and data-reduction techniques are used to rapidly assess the quality of a state-of-the-art VLSIC fabrication process, to detect and locate process problems accurately, and to evaluate the component yields of IC chips fabricated by the process. This is accomplished by decomposing the basic building blocks of an IC (the transistor and its interconnections) into their elemental parts and evaluating their electrical properties separately and in concert by means of specially designed test structures. Specific causes of electrical faults are inferred from the data obtained from these structures. Other test structures provide parametric data for process monitoring and circuit-performance analysis. This methodology and these tools simplify considerably the difficult task of VLSIC fabrication process assessment, problem diagnosis, and yield analysis.