Improve The Door Of The Unit Input Jump Current Source Model And Its Application In Ssta

The integrity problem of the voltage signal brings serious challenge to static timing analysis (STA) with IC technology’s continuous development and entrance into the nanometer era. The traditional STA based on the delay look-up table can only handle ideal ramp input voltage and simple capacitive load for logic gates, while it cannot address the problem of non-linear input voltage and complex interconnect load. The current source model which can nicely deal with the non-linear voltage signal has been broadly used in the timing analysis tools of the industry. The phenomenon of multiple input switching further complicate the timing analysis since simply taking it as the single input switching can introduce significant error.Meanwhile the process variation is more pronounced with the more complex manufacturing procedure. The variation of physical and electrical parameters for devices and interconnects, and that of the operating voltage make the longest path of the chip a random variable obeying some type of distribution instead of a fixed quantity. The statistical static timing analysis considering process variation gradually replaces the traditional STA and become the analysis tool for yield and frequency distribution of chips with nanometer feature size. The popular SSTA scheme taking the circuit delay as random variable has been very mature, however both the signal integrity and multiple input switching are ignored.To address these problems, this paper first demonstrates the parasitic coupling capacitance between input and internal nodes of gates and theoretically analyzes its source. We improved the existing multiple-input-switching current source model and waveform simulation accuracy by introducing the Miller capacitance between gate’s input and internal nodes. The model is extended to gates with multiple inputs so that a complete advanced multiple-input-switching current source model (AMCSM) is constructed. On the other hand, the paper proposes a fast gate-level SSTA method based on AMCSM and sampling strategy. We applied the Data Reuse Incremental Analysis Method (DRIAM) to raise the computational efficiency on varied process corners.The experimental results demonstrate that compared with the existing model, AMCSM achieves more than better simulation accuracy for delay and output waveform of gate cell. Among various gate cells, the maxium delay error is around6%. The gate-level SSTA has comparable simulation accuracy with SPICE, the average relative error of50%Vdd voltage arrival time is within0.6%and that of the deviation is within4%. By using DRIAM, the computational cost of SSTA is reduced by7times on average.