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Research Of Signal Integrity Problem In Deep Submicron VLSI Design

Posted on:2006-12-12Degree:MasterType:Thesis
Country:ChinaCandidate:J XuFull Text:PDF
GTID:2178360185496977Subject:Computer system architecture
Abstract/Summary:PDF Full Text Request
Signal integrity is refered to a state that signal is not degraded. It represents signal quality and correct functional characteristic during signal transfers. Good signal integrity requires that signal can response with proper timing and voltage when necessary, and if lacking such ability, signal integrity problem emerges.Narrowly, signal integrity problem consists of crosstalk and IR-drop; Generally, it still includes power-net electromigration, signal-net electromigration and hot-carrier effect. Among them, crosstalk noise caused by coupling capacitance is the most dominating signal integrity problem on chip. It not only affects circuit delay, causing setup time and hold time violation, but also destroys circuit function, resulting in chip failure.As technology scales into the deep submicron regime, analog phenomenon is enhanced on digital chip, and the most important effect is that signal integrity problem becomes more and more servere. On the other hand, the requirement for higher performance and faster frequency makes signal integrity problem unneglectable. Today, signal integrity problem with power consumption turns into primary bottleneck limiting continued advancement of VLSI design.This paper firstly introduces hot research field about crosstalk noise such as model building, computing technique, prevention and fix method, then takes the emphasis on the flow implementing signal integrity of Godson-2 CPU memory module. The paper compares the accuracy and speed of two famous crosstalk analysis tools: PrimeTime SI and CeltIC, and measures a set of data corresponding with signal integrity problem at 0.13μm technology, including the correlation between coupling capacitance, driving strength, signal transition time and crosstalk noise. Finally this paper produces a successful methodology addressing signal integrity through completing physical design of memory module. The experiment proves that the methodology not only meets accuracy of 0.13μm but also spends less run-time, ensuring the deadline of tape-out validly.
Keywords/Search Tags:signal integrity, crosstalk, function noise, delay noise, coupling capacitance, static noise analysis
PDF Full Text Request
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