VLSI Design Of Equalizer For60GHz Communication System

The up to7GHz unlicensed band for60GHz systems draws widespread interest. Assupporting data rate up to Gbps in indoor short-range(≈10m) communication,60GHzcommunication may be a replacement of wired High Definition MultimediaInterface(HDMI) and may find its application in intra-vehicle networks.However, the realization of60GHz system also confronts great challenges. Thesevere indoor multipath effects may introduces inter-symbol interference spanningabout100symbols. So a channel equalizer becomes a necessity. As the number of tapsof multipath channel is large, the complexity of frequency domain equalizer is muchlower than time domain one. Moreover, with very low cost, this frequency domainequalizer in Single Carrier(SC) mode can be changed to a SC/OFDM dual modeequalizer which can be switched between SC mode and OFDM mode.The frequency domain equalizer in SC mode contains one FFT processor and oneIFFT processor. The two are of the highest computation complexity so they are the keyof the performance of the equalizer. In order to support the throughput rate of2Gbpsand clock rate of250MHz, a parallel structure with8paths is proposed here. The radix-2~4-2~2-2~3decomposition algorithm is devised to reduce the multiplication computationcomplexity. Moreover a three-stage pipeline structure is also proposed to implement themultiplication between the512-point twiddle factor and the output of the butterfly of thefourth step, which reduces the number of CSD-coded constant from512down to17. Areordering scheme is developed to convert the parallel results from bit-inverse order intonormal order, so the output of the FFT processor can be directly fed to the next IFFTprocessor. To improve the SQNR, outputs of every step of the FFT structure is scaled by1/2which considerably attenuates the quantization noise produced by the former stagesand enhances the SQNR to45dB with the internal data width of14bits.The function of the proposed FFT and equalizer structure is verified by dynamicsimulation. Then synthesis, place and route is completed with target device of Virtex7FPGA and the timing closure is reached, so realization of this structure on FPGA isverified. At last, ASIC front-end flow is complete with SMIC0.13us target process. So it is safe to conclude that the equalizer structure is totally verified and implemented andthe proposed FFT/IFFT structure is suitable for the SC/OFDM dual mode equalizerunder IEEE802.11.ad standard.