The Front-End Design Of An IFFT/FFT Processor For UWB Applications

With the interinfiltration of Internet,multimedia and wireless communications technologies,high-speed,high-quality,short-range wireless multimedia data transmission has become an urgent demand,so a new concept-Wireless Personal Area Network (WPAN)came into being.WPAN refers to the so-called having the ability for interior, office and other consumer electronics equipment and computers to provide short-range, high-speed multimedia data services.Multi-band orthogonal frequency division multiplexing ultra-wideband(MB-OFDM UWB)standard is to meet the requirements of the most popular WPAN technology.As a modulation technique in MB-OFDM UWB system,OFDM not only has reliably high-data-rate transmission but also can provide high spectral efficiency.The IFFT/FFT processor is key to OFDM modulation.The data sampling rate of FFT processor in MB-OFDM UWB standard is up to 528Msample/s or higher.Moreover,the IEEE 802.15.3a Task Group has also been formed to develop a solution providing over 2Gbps data rate,which makes the design of FFT processors an enormous challenges.This dissertation makes research in designing an IFFT/FFT processor in MB-OFDM UWB system.This dissertation presents a high-throughput,hybrid word-length,mixed-radix,four -parallel data-path 128-point IFFT/FFT processor for MB-OFDM ultrawideband(UWB) systems.The proposed processor uses an error compensation method for modified Booth fixed-width multipliers and canonic signed digit(CSD)multipliers,which leads to higher precision and lower hardware complexity.From analysis,it is shown that the proposed architecture makes the best balance of the precision,the hardware cost and the speed.So it can fully meet the requirements of Gigabit(gigabit)WPAN.Meanwhile,the dissertation also discusses a modified radix-64 FFT processor which can be of occupying with less resources and control of the characteristics of simpler than other radix-4 pipeline architecture.In order to efficiently accommodate large input data sets,large input data range,high precision and high speed in real time,combining the feature of easily expanding of radix-64,an improved architecture of radix-4 can further reduces the number of complex adders and improves the processor clock frequency.