Fft / Ifft Processor Suitable For Lte Wimax Wlan System And Its Vlsi Implementation

With the lifestyle changing, the wireless communication plays an important role in our life. The orthogonal frequency division multiplexing (OFDM) has excellent bandwidth efficiency and invulnerability to non-ideal channels, so it usually applies in the wireless communication system. And the fast Fourier transform (FFT) is the key module for the hardware implementation of OFDM.In this thesis, a high efficient FFT processor is proposed. The FFT processor supports three systems, LTE, WiMAX and WLAN, and resolves the difference of three wireless communication systems in an efficient way. With the employed FFT algorithm, the proposed architecture can support 128/64-point FFT for for IEEE 802.11n WLAN, and 128/256/512/1024-point FFT/IFFT of for WiMAX and 128/256/512/1024/1536/2048 FFT/IFFT for upper link and down link in LTE system. For an efficient transformation of three systems, the single-path delay feedback (SDF) is introduced into the mixed-radix architecture of FFT/IFFT calculation, which can gain higher hardware efficiency, higher data throughput rate and lower memory consumption.The proposed FFT processor is implemented by SMIC 0.13um process, and the area is 1.8×1.8 mm2. It is area efficient for VLSI implementation.The main contribution of this dissertation can be concluded as following:(1) Analysis on FFT/IFFT alrorithm, comparing two main algorithm, Cooley-Tukey algorithm for the common use and PFA(Prime Factor Algorithm) for prime factor. Furthermore, based on the hardware implementation of the two algorithms, their advantages and disadvantages is compared.(2) Based on the algorithm mentioned above, the hardware architectures of various algorithms are analyzed. The hardwares are categolized into two main architectures, the memory-based architecture and the pipeline architecture. Furthermore, different structures on pipeline architecture are compared according to different radix-split algorithm. According to different applications, the pros and cons of different structures are scrutinized, based on hardware consumption, design complexity, power consumption, and troughput rate.(3) Based on the analysis above, a proposed FFT/IFFT processor is designed for three systems, LTE, WiMAX and WLAN. With the employed FFT algorithm, the proposed architecture can support 128/64-point FFT for IEEE 802.1 In WLAN, 128/256/512/1024-point FFT/IFFT for WiMAX, and 128/256/512/1024/1536 /2048-point FFT/IFFT for upper link and down link in LTE system. Especially, the architecture can support 2n FFT calculation and radix-3 FFT with share elements of memory. Employing the PFA split algorithm, multiplications between stages of calculations can be significantly saved than in Cooley-Tukey algorithm. With the employed FFT algorithm, the proposed architecture can support 128/64-point FFT for IEEE 802.11n WLAN, and 128/256/512/1024 FFT/IFFT for Wi-MAX and 128/256/512/1024/1536/2048 FFT/IFFT for upper link and down link in LTE system. For an efficient transformation of three systems, the single-path delay feedback (SDF) is introduced into the mixed-radix architecture of FFT/IFFT calculation, which can gain higher hardware efficiency, higher data throughput rate and lower memory consumption.(4) The summary of the proposed architecture is explained in the last chapter of this dissertation, and a analysis of the fixed-point simulation of the SQNR(signal quantization noise ratio) is analyzed by comparing the differences of wordlength. The proposed FFT processor is implemented by SMIC 0.13um process, and the area is 1.8×1.8mm2, the highest working clock frequency can reach 300MHz, the data throught rate can meet the requirement of the proposed communication system at the working clock rate.