Design Optimization And VLSI Implementation Of Equalizer In OFDM System

Orthogonal frequency-division multiplexing (OFDM) technique has become a hotspot in the field of research because of the ability to provide the high-speed rate and high-quality communication service. One problem that must be faced in the design of wireless OFDM systems is that the signal symbols are interfered by the channel when transmitted through the communication media. The equalizer in OFDM systems is used to remove the impacts of multipath channel via signal processing in order to guarantee the receiver to estimate the transmitted data successfully. Thus, the proper algorithm and design of equalizer are very important for the whole system, which are focuses of this thesis.After the introduction of the general research background, the research state and implementation of the equalization technique in OFDM systems are summarized in two aspects. The first aspect is about the VLSI design of one-tap equalizer when enough cyclic prefix (CP) is used, and another aspect focuses on the study and implementation of the equalization scheme while the CP is insufficient. The following are the main propositions in this thesis:In OFDM-based IEEE 802.11a Wireless LAN, the conventional design of one-tap equalizer does not consider the different requirements of the modulation schemes. In order to make the system to work well in all modulation schemes, the hardware design of the equalizer is targeted to the modulation scheme with the highest requirement. Such an equalizer can satisfy the system requirements when other modulation schemes are used, but the excessive operations waste time and power. Based on the study of the four modulation schemes adopted in IEEE 802.11a standard, the structure of adaptive-modulation-oriented configurable one-tap equalizer is proposed. The configurable one-tap equalizer has two states and provides the appropriate equalization way for a certain scheme. Since the unused part of circuit can be shut down, the power dissipation of the configurable one-tap equalizer decreases significantly when the system works in lower modulation schemes. In the circuit design of configurable one-tap equalizer, a dual-mode CORDIC processor is used to accomplish rectangular-to-polar conversion and vector rotation at different periods of time, which reduces the hardware scale of the equalizer. With TSMC 0.18μm CMOS standard cell process, the configurable one-tap equalizer uses about 42k equivalent gates without considering RAM at clock frequency of 20MHz. Under high-level modulations and low-level modulations, the circuit's powers at the initial stage are 2.2mW and 1.4mW, respectively, and the running powers are 1.8mW and 1.4mW, respectively.Next, making use of the new architecture of configurable one-tap equalizer, FFT processor, one-tap equalizer, and phase tracker, as three concatenated blocks in IEEE 802.11a receiver, are co-designed. The twiddle factor processing is one of the most complex calculations in FFT processor. The CORDIC algorithm is adopted to implement the twiddle factor processing in this thesis, and it is proposed to merge the magnitude correction factor in CORDIC algorithm into the magnitude equalization in configurable one-tap equalizer, which saves the hardware resource for FFT processor remarkably. Based on single radix-2~3 processing element, the circuit scale of FFT processor is about 318.4k gates, and the power dissipation is about 24mW. At the same time, it is introduced to combine the phase tracking and the phase equalization of configurable one-tap equalizer. By combining two continuous phase rotations, the co-processor performs both phase equalization and phase tracking with small additional hardware beyond configurable one-tap equalizer.When CP is insufficient, the simple one-tap equalization cannot counteract the interferences of channel properly. Considering that conventional residual inter-symbol interference (ISI) equalization techniques have the drawback of high computational complexity, three low-complexity methods are presented in this thesis. In the first method, based on the observation that only a few samples in the time-domain signal symbol are contaminated by residual ISI under typical wireless LAN channels, the zero-forcing decision-feedback equalization (ZF-DFE) method using cyclicity restoration (CR) is derived, which offers evidently less computational complexity than conventional ZF-DFE while giving the same performance. Then, in order to avoid the complex matrix inversion in ZF-DFE method, the frequency-domain iterative equalization method and the time-domain iterative CR method are proposed. Inspired by the multiple access interference mitigation technique in code-division multiple access system, the frequency- domain iterative equalization method is proposed, which cancels the inter-carrier interference (ICI) induced by residual ISI in frequency-domain. The time-domain iterative CR method is based on CR method and mitigates residual ISI by an iterative style in time domain, which provides very low iteration computational complexity. After the introductions of these three methods, the performance and complexity comparisons among the various methods are made as the groundwork of algorithm choosing for the design of residual ISI canceller.Finally, on the grounds of the study of relations between all iterative methods, the combined iterative method using transform-domain and time-domain methods is proposed in order to achieve both low implementational complexity and low iteration complexity. After the implementation analysis of the combined iterative method, the VLSI design of the combined iteration processor is completed. The processor performs iteration matrix calculation, ISI cancellation and time-domain iteration with the same processing core at different periods of time. At clock frequency of 20MHz, the average power is 20.7mW.