Ofdm Uwb Systems, Low-power, Low Complexity Degree Of Digital Signal Processing And Vlsi Implementation Of The Method Of Study

The explosive growth of the modern multimedia technology and its corresponding consumer electronics equipments, such as high-definition television (HDTV), digital home theater, high-fidelity digital audio, smart phone, lat-top, set-top boxes and gam-ing stations, have recently convinced and promoted a brand new market for wireless applications:the wireless personal area network (WPAN). Ultra-Wide Band (UWB) has become the preferred technical solution for the next generation WPAN, due to its high data rate, flexible spectrum utilization, low energy consumption, low cost, less interference and the characteristic of strong anti-interference. The UWB has received many attentions since the Federal Communication Commission (FCC) formally ap-proved in 2002 to allocate 7500 MHz of spectrum for unlicensed use of UWB devices. The multi-band orthogonal frequency division multiplexing (MB-OFDM) based UWB has been adopted by the European Computer Manufacturers Association (EC-MA)/International Standards Organization (ISO) standards and has recently been se-lected as physical layer solution for high speed wireless connections such as Wireless Universal Serial Bus (W-USB), Bluetooth 3.0 and Wireless High Definition Media Interface (W-HDMI). Chinese government issued its UWB spectrum plan in 2008, and started the standardization works after. The Chinese UWB standard applies the dual-carrier OFDM (DC-OFDM) technology.There are three key challenges for the practicality of UWB technology:1) the large power consumption and the high cost have seriously limited the use of UWB chips in hand-held devices and consumer electronics applications; 2) A higher data transmis-sion capacity is urgently required to match the rapid development of multimedia technology and to face the fierce competitions with other innovative wireless tech-nologies, such as IEEE 802.15.3c and IEEE 802.11n; 3) To the promotion of globali-zation, the UWB devices should be compatible with standards in different regions. Aiming to tackle the above issues, this dissertation studies the key technologies of digital signal processing and VLSI design for OFDM-UWB system. We have imple-mented several low-cost, power-efficient and high performance signal processing modules and developed a dual-mode UWB digital baseband that can seamlessly sup-port both the MB-OFDM and the DC-OFDM technical specifications. The FFT/IFFT processor is responsible for the OFDM (de)modulation in UWB system and is one of the key modules playing a critical role in system reliability and area/power efficiency. We propose an eight-path delay feedback (EPDF) VLSI struc-ture to implement the 8x8x2 mixed-radix algorithm. Together with the multiplier-free twiddle factor calculation unit, the EPDF structure can efficiently improve both the data throughput and the hardware utilization with significantly reduced power. The fabricated FFT/IFFT chip represents 49% energy efficient and 53% more area effi-cient than state of the art in the open literature.To solve the serious front-end non-ideal effects in low-cost UWB implementations, this work analyzes the joint impacts of the carrier frequency offset (CFO), the sam-pling frequency offset (SFO) and the I/Q imbalance. We propose, for the first time, a complete solution for these three non-ideal effects, including a time-domain CFO es-timation algorithm that can efficiently avoid the I/Q imbalance interference, a I/Q imbalance estimation algorithm on partial phase compensation, a two-step joint CFO and I/Q imbalance compensation scheme as well as a frequency-domain high preci-sion SFO and residual CFO estimation and compensation method. This package of algorithms guarantees the reliability of the wireless link in low-cost UWB chips.The multiple-input multiple-output (MIMO) technology has been seriously consi-dered for the next-generation ultra-high speed UWB system. This work designs the signal detector at the receiver side. At the algorithm level, we introduce a low com-plexity early-pruned K-Best signal detection algorithm. At the VLSI architecture level, we develope a parallel multi-stage folded architecture that can seamlessly support various configurations in terms of antenna number and modulation order. Meanwhile, we propose three techniques to further improve circuit efficiency, including candi-date-sharing structure, two-stage sorter and real-value zigzag enumerator. We imple-mented an MIMO signal detector at 130μm node. It can support 2×2/3×3/4×4 MIMO and QPSK/16-QAM/64-QAM modulation configurations. Measurement results suc-cessfully demonstrate a 1.1Gb/s detection throughput and 115 pJ/bit energy consump-tion. To the best of our knowledge, this is the fastest and most energy efficient among all the MIMO detectors reported in the open literature.Finally, we design the signal processing algorithm, the VLSI architecture and the timing plan for a dual-mode UWB digital baseband chip based on a comprehensive analysis of the UWB standards. After demonstrating the detailed signal processing block reuse information, we have developed a FPGA verification and demonstration platform for UWB system. The proposed UWB digital baseband has been synthesized using 0.13μm CMOS technology. The implementation results illustrate that the algo-rithm and circuits structure proposed in this dissertation can meet the design specifi-cations quit well and thus it is believed to have a promising potential for practical ap-plications.