Design And Implementation Of The Digital Circuiy In The SerDes Chip Based On IEEE1394b

As the growing demand for the high-speed data transmission, SerDes technologywhich is applied to the design of high speed serial interface attracts increasing attentionnowadays. SerDes technology is a kind of time division multiplex technique. Byconverting multi-channel low-speed parallel signal into a high-speed serial signals, itcan make full use of the channel capacity and reduce the communication cost. Inaddition, as a kind of serial communication technology standards, IEEE1394b supportshigh-speed access, peer-to-peer communication and hot swapping and so on.As a high-speed serial link, SerDes has complex circuits and involves both analogand digital parts.The target of our project is to design an SerDes chip based on IEEE1394b protocol, I am responsible for the realization of the digital module of SerDes.This article first introduces the structure and digital modules’ function of SerDes basedon IEEE1394b protocol, then establishes the design of digital circuit through atop-down design methodology. By analyzing the protocol, digital modules’ functionalmode and technical specifications are primarily defined, technical specifications andimplementation techniques of each sub-module are determined following the division ofthe entire circuit into several sub-modules. Then Verilog HDL is employed to fulfill thedigital modules’ RTL modeling. Finally the RTL level circuits are verified by thefunctional simulation tool, Modelsim.Take into account the problem of chip testing, IIC Slave controller and built-inself-test circuit are designed in the SerDes chip. By reading and writing control signalsfor modules in the SerDes chip, IIC Slave controller can select different modes to testthe chip. And the built-in self-test circuit can complete chip key module testing andanalysis of the test results. The circuit consists of two modules, a test vector generationmodule and a test data analysis module.These test circuits help us simplify the difficultyof chip test and improve the test efficiency of key modules in the SerDes chip.Based on the RTL level circuits of the digital modules, the paper used amethodology of standard cell based to complete the digital modules’ ASIC implementation. First of all, through logic synthesis the RTL code is transformed intothe gata-level netlist. Then formal verification and static timing analysis are used toverify the validity of the gata-level netlist. After verification results correctly, we use ICCompiler to complete the layout design and use VCS to complete post-simulation in theprocess of design. Finally, the SerDes chip is implemented by SMIC0.13μm CMOSprocess, which die size is2.9*1.6mm2.