The Design And Implementation Of A Frequency Synthesizer Based On A1-GHz Phase Locked-loop

The frequency synthesis technique has been widely used in moderncommunication-electronic equipment. The frequency synthesis method based on phase-locked loop (PLLFS) is an indirect way among all the synthesis techniques, but it canprovide a large number of stable and pure frequencies, and take so small chip area that itcan be easily fully integrated onto a chip. In the past decades, a lot of development hasbeen made on this technique, and it has become the dominant trend. The noise from thevoltage-controlled oscillator (VCO) and the reference signal can be suppressed in thephase-locked loop (PLL). As more wireless/radio-frequency (RF) systems apply formore stringent requirement, such as narrower channel steps, lower phase noise, higheroutput frequency and shorter settling time, there are more challenges the PLLFS has todeal with.The PLLFS first mentioned in this article will be applied to a serialize/deserialize(SerDes) circuit which is a critical part of the IEEE1394b physical (PHY) system. Tofulfill the need of the system, a3-order2-type charge pump-based PLL (CPPLL)topology is chosen. The input reference frequency is25MHz. The transfer functions arefigured out in the frequency domain, and then the behavior models are built to decidethe key loop parameters and make the jitter simulation time-efficient. The chip can besettled in5μs, providing4-phase differential1GHz clock signal and100MHz squarewave clock signal. The chip area (without pads) is0.12mm2, and the current consumedis22mA. The measured root mean square (RMS) value of period jitter of the PLL’soutput100MHz clock signal is78.15ps. Because of the lack of experience, theperformance of this chip still remains to be improved.The second PLLFS is a sub-sampling (SSPLL) type, which can change thesituation that the in-band noise can be magnified by the squared frequency dividing ratioin the CPPLL loop. So the SSPLL’s in-band noise is further suppressed and its designcan take advantage of the behavior models and main circuit blocks of the CPPLL. It cangenerate the same clock signal as the CPPLL in the required time. The VCO’s topologyin the SSPLL is self-biased type and it will further reduce the impact of the power supply noise. There is no frequency divider in the SSPLL’s core loop, and a sub-sampling phase detector works with a transconductance charge pump to detect the phasedifference. The key loop parameters are determined in the same way as in the CPPLLloop.