Design Of Low Power Asynchronous LDPC Decoder

The performance of LDPC (Low Density Parity Check) code is excellent. It has a lot ofadvantages, such as close-to-Shannon-Limit decoding performance, low decoding complexity,strong error correction and detection ability, large throughput, simple and flexible hardwarerealization. As a result, LDPC code has become a research hotspot in the field of channelcoding, and has been widely used in the fields of communication and broadcasting. However,the application of modern mobile communication needs the modern mobile terminals tosatisfy the low power consumption requirement. From the perspective of both the decodingalgorithms and hardware implementation, it is important to realize the low power LDPCdecoder.Nowadays, as the IC (integrated circuit) design has stepped into the deep sub-micronprocess technology, low power design has become an important direction in thesemiconductor industry. Synchronous circuit design was the mainstream in a long-term ICdesign, but it faces the challenges on how to achieve low power system, how to improve chipperformance, how to strengthen the anti-interference ability, and etc. Asynchronous circuit hasgradually been found more potential in many ways compared with synchronous circuit,especially on reducing power consumption.Therefore, a low power asynchronous LDPC decoder was proposed based onasynchronous circuit design methods in this thesis. The main innovative work of this thesiscan be summarized as follows:1. Method of control path and data path hybrid-connection and the design process of lowpower asynchronous LDPC decoder were proposed based on separation design in view of theexisting asynchronous circuit design methods and EDA design tool. Control path wasdesigned according to the specific handshake protocol, using handshake components. Datapath was proposed by synchronous/asynchronous hybrid functional modules, as well as somematched delay circuits. The hybrid-connection design method not only avoids complicatingthe system caused by matching delay circuits, but also simplifies custom design of fullasynchronous data path.2. Key modules of asynchronous LDPC decoder’s control path were proposed. The symmetric structure was verified to be the best one of four different C elements. Thesymmetric set-C unit was designed to constitute the full coupled latch controller with aninverter, realizing four phase bundled data protocol asynchronous pipeline.3. Key modules of data path of asynchronous LDPC decoder, such as adder, comparator,and multiplexer were proposed. Asynchronous carry lookahead adder was proposed withdual-rail carry-out signals and single-rail sum signals. The asynchronous pre-stop comparatorswith static and dynamic logic were introduced based on input data statistical characteristic.They can “pre-stop” operation and output the comparison result at the first unequal bit.Aynchronous MUX was presented to optimize the connection between different key modules,reducing glitches and redundant computations, so it can reduce power consumption.4. Both the synchronous and asynchronous LDPC decoder were implemented with SMIC0.18μm CMOS process, and they were simulated under1.8V supply voltage and25℃.Results showed that the asynchronous design consumes16.33%less power compared tosynchronous design. It proved the power efficient characteristics of asynchronous LDPCdecoder.In conclusion, with the potential power efficiency of asynchronous circuit design, fromthe research of low power consumption IC design process and techniques, key modules ofLDPC decoder’s control path and data path are proposed. And the overall asynchronousLDPC decoder is implemented, meeting the low power consumption requirement.