Long Constraint Length Viterbi Decoder Hardware Design And Implement With Low-power Design Technology

Convolutional coding is a coding scheme often employed in deep space communications and recently in digital mobile communications. The Viterbi algorithm is known to be an efficient method for the realization of maximum likelihood probability (MLP) decoding of convolutional codes. The wireless cellular standards for CDMA and WCDMA, IS-95 and 3GPP employ convolutional coding as channel enor conect coding for real time business. In these standards, the constraint length equal 9, with the exponential proliferate of the hardware complex and large power dissipation, the Viterbi decoder become difficulties to implement, and the power dissipation is become the bottle-neck of Viterbi decoder application in wireless communication.In this thesis, we investigated a low-power design of Viterbi decoders that constraint length equal 9. In CMOS technology the major source of power dissipation is attributed to dynamic power dissipation, which is due to the switching of signal values. The focus of our research in the low-power design of Viterbi decoders is reduction of dynamic power dissipation at Register Transfer Level (RTL). We analysis the architecture of the Viterbi decoder, optimize some modules with low-power design technology. There were several methods on the following is very important in this thesis. ACS module adopts 4 ACS units to do parallel computing, properly organize the order of data reading/writing to path metric memory. In path metric update, we adopt In-place path metric updating method that can reduce half of memory space, and lower the power dissipation. In path metric memory management method, we partition the whole memory into 4 banks, every ACS unit read/write the two bands memories accordingly. SMU module adopts the clock-gating method was applied to the survivor path storage block, reduce the survivor path storage memory power dissipation effectively.In this thesis we use bottom up design method, implement the function modules and integrate all mudules to the whole Viterbi decoder, We describe this design in Verilog HDL, and use the simulation and synthesis tools implement the verification of this Viterbi decoder. Finally, use the Xilinx FPGA development tool to implement this design and the power analysis.