Design And Verification Of SoC PLB Bus And Relevant Module

The efficiency of the bus and its interface determines the efficiency of the SoC. Not onlydoes the inefficient bus affect the communication performance between various modules inthe system and weaken the performance of the total system, but also would take up a lot ofresources on the limited on-chip system. Processor Local Bus is the most important part ofCoreconnect bus, which is developed by IBM. At present, the technology of PLB is primarilymastered by foreign companies. In order to develop the core technology of independentintellectual property rights, and to pave the way for future applications, this paper studies PLBbus for engineering.The main work of this paper is to design PLB bus interface and bus control modulebased on the slave units of PCI bus and memory. Firstly, analysis and comparison between5kinds of bus specification on current market were made. Next PLB bus protocol and thestructure and mechanism of PLB bus interface were closely studied. Then, based onunderstanding the timing of PLB bus and working mechanism and function of thesub-modules within this paper, the PLB bus module, DMA module and bridge module weredesigned, whose functionality were achieved by using Verilog hardware description language.At last, the read and write functions of the system were validated and analyzed after buildingPLB bus interface testbench, and proposed feasible verification strategy.Results show that the PLB bus read and write module can meet requirement of theapplication environment, also be able to complete read and write functions.