Design And Implementation Of An SPI Function Simulation Verification Platform Based On UVM

In the past two years,microelectronics technology has developed rapidly,and the level of chip design has been continuously improved.Traditional verification methods have been unable to meet the current verification needs,and functional verification is gradually facing huge challenges.UVM is a new type of verification methodology with high efficiency,versatility and reliability.At the same time,the UVM verification platform can be reused and easy to maintain,so it has become one of the most effective verification methodologies.The main content of this thesis is to design the SPI interface controller module,and use this module as the DUV to build a UVM function verification platform that supports coverage and randomization.Firstly,the structure,timing and functional features of the SPI controller module are analyzed in depth,and the Vertilog HDL hardware description language is used to complete the RTL code implementation of the circuit module.Secondly,the function points for verification are extracted according to the functional features of the SPI module,of which the main function points for verification include: register read and write and stability,asynchronous FIFO normal read and write and boundary state,finite state machine state transfer and timing control,and data transmission format.Finally,formulate a verification plan,and according to the formulation plans to build the various components of the UVM verification platform,perform a comprehensive simulation of the function of the SPI controller system module by creating 12 testcases,and collect coverage at the same time as the functional simulation.In addition,this thesis adds assertion-based verification(ABV)to the UVM verification platform to improve the adequacy of verification.In order to ensure the correctness of the internal wiring of the system module,this thesis selects the formal verification method based on property-assertion to check the connectivity of the system module of the SPI controller.During the simulation of the UVM verification platform,four important design defects were found,and they were recorded and a defect curve was drawn.After defect repair and regression testing,the final defect curve gradually converged,and the function coverage reached 100%,the assertion coverage was 100%,and the revised code coverage also reached 100%.All 12 testcases created in this thesis finally passed,and the 25 properties defined are all asserted successfully.The connectivity check through formal verification also proves that the system's asynchronous reset signal is correctly connected.The simulation results show that using UVM verification platform can improve the efficiency of functional verification,and at the same time can ensure the completeness and credibility of the verification results.The final simulation results have met the sign-off requirements of functional verification and can be accepted.