| With the rapid development of integrated circuit technology, integrated circuitdesign scale and complexity is increasing, leading to verify workload exponential modelgrowth. Especially the functional verification of a chip，as the most key steps in a chipdesign,has become a bottleneck in the development of integrated circuit, so how toimprove verification efficiency, increase the level verification reusability becomeintegrated circuit industry unsolved problem.This paper firstly introduces the research status of the integrated circuit industry,analysis and discussion of the main means of verification, and compares advantages anddisadvantages. And then by compared other verification language and SystemVerilog,explain the advantage of the the SystemVerilog language hierarchical verificationplatform in the integrated circuit verification Then illustrate SystemVerilog OVMverification method, elaborate the OVM verification platform modeling and OVCS.This paper takes a TDM module for an example,based on SystemVerilog andOVM methodology to develop specific verification scenarios and build a hierarchicalverification platform. The verification platform built not only to verify the efficiencyand reusability, and can be re-used for other similar functional verification module. |
