Design And Implementation Of PUF Circuit Based On SystemVerilog

Since entering the 21 century,the information industry has been rapidly developed,intelligent products quickly into people's lives and work.However,the continuous progress of information technology brings higher challenges to hardware security,and the traditional information security technology is difficult to satisfy the requirements of the market,so the new hardware security technology has become the subject of current research.According to the unique physical differences of hardware devices,the Physical unclonable functions becomes a new type of hardware security primitive,which can effectively resist physical attacks.PUF is different from functional relationship in the mathematical sense.The latter mainly produces mapping relations of functions through logical operations,but PUF uses the process deviation of the IC in the manufacturing process to produce mapping relations of CRPs.The security key of the hardware is usually generated by the response generated by the PUF.Because of the uncontrollability and randomness of this process deviation,the device with PUF is born with unique physical random characteristics,so PUF is called the fingerprint of hardware.PUF has a good application prospect in many security fields such as device authentication,chip encryption,secret key storage,ID protection and intellectual property(IP)protection because of its unique physical random characteristics.Arbiter PUF is one of the implementation methods of digital PUF.It has been widely used and studied because of its simple structure,small area,low cost and more "excitation-response" peer advantage.In this paper,the design and verification of the Arbiter PUF are studied in depth.This paper expounds the PUF in detail from the basic concepts and principles of PUF,and deeply studies the characteristics,classification and typical structure of implementing PUF.Aiming at the current mainstream digital PUF circuit,the Arbiter PUF is chosen as the research object of this paper.Firstly,the design of each module of Arbiter PUF circuit is completed by hardware language.Aiming at the problem that the layout and wiring could strictly guarantee the complete symmetry in the later stage,the paper proposes that the non cross coupling multi-channel selector switch is used instead of the traditional cross coupling switching unit,which improves the physical randomness and stability of the output response of the Arbiter PUF of the arbitrators.Secondly,this paper analyzes the System Verilog verification language in detail,introduces its advantages as the mainstream language in the current verification field,and expounds the Universal Verification Methodology and relevant mechanism.In order to verify the correctness of the design,the verification platform of Arbiter PUF based on UVM is written in System Verilog language.The stability,uniqueness and uniformity of the Arbiter PUF circuit are verified and tested,and the coverage is collected.Finally,through the analysis of the experimental results,the stability value of the Arbiter PUF circuit is 2.77,the unique value is 49.06,and the uniform value is 50.06,which is very close to the ideal value.Compared with similar papers,the characteristics of the arbiter PUF circuit are greatly improved and optimized.Therefore,it is proved that the delay-based arbiter PUF achieved the design goal.Code coverage reached 98% and function coverage reached 100%,FSM coverage reached 100%,which achieved the purpose of verifying the Arbiter PUF circuit.