Verification Of An Image Scaler RTL Model With A Testbench In SystemVerilog

System-On-Chip has been used pervasively in many areas due to the sharply risingscale of integrated circuit in the context of the booming semiconductor industry.Whereas, chip verification, especially functional verification is still an unresolvedchallenge that corresponding to approximately the70%of the lifecycle. Thus,traditional verification methodology is becoming a bottleneck of the SOCdevelopment project. An advanced verification methodology is needed to achieve thesuccess of the entire SOC development project.This Master’s thesis reports the verification planning and process of a Verilog RTLModel which is a key component in the Digital TV SOC. The main task of thisverification project is to ensure the design specification and functional requirementsof image scaling is implemented completely.First of all, the history of verification methodology is briefly reviewed, anddiscussing the challenges that design verification faces. The thesis gives a specifyintroduction to techniques commonly used in the verification process such asconstrained randomization, functional coverage, code coverage and layer architectureetc., and gives the necessary background for the verification planning andimplementation described in later part.Secondly, the verification plan of image scaling module which plays an importantrole in Digital TV SOC was laid down by analysis the design specification andfunction points. The testbench was designed and implemented on the base of thoseprinciples that is hierarchical, reusable and randomized by using SystemVerilogLanguage and advanced verification techniques according to the verification plan. Thedetail of the overall verification process and environment is also specified.Finally, the image scaling module verification project was demonstrated to achievesuccess by analysis the verification result and revealed high code and functionalcoverage. In addition, the testbench can conveniently be used to system-levelverification, and as a reference for relevant projects.