Design And Implementation Of The IEEE802.16e LDPC Decoder Based On FPGA

Since being rediscovered in1990s, Low Density Parity Check Code (LDPC)codes have attracted people’s attention and have become another research focus ofchannel coding community after Turbo codes because of their approaching to theShannon limit error correction performance and the advantages of low decodingcomplexity and high decoding throughput. Today, LDPC codes have been widelyapplied in different communication systems such as DVB-S2, CMMB and WiFi. LDPCcodes are the channel coding scheme in the IEEE802.16e standard. In this thesis, theField－Programmable Gate Array (FPGA) design and implementation of the LDPCdecoder for the IEEE802.16e standard is discussed.Firstly, the most common Belief Propagation decoding algorithm(BP for short) ofLDPC code is discussed, and Log-Likelihood Ratio Belief Propagation (LLR-BP) ispresented. And it is compared that the performance of BP algorithm with LLR-BP bysimulation, the performance of the LDPC codes and convolutional code is also simultedand analyzed. Simulation results show that the LLR-BP algorithm and BP algorithm isof the same performance however the performance of the LDPC code is superior tothe convolutional code. Combining with the characteristics of FPGA, the partial parallelstructure is selected as the basic structure of the LDPC decoder, and the sub-modulestructure design of the decoder is proposed in this thesis.