Investigation Of Ldpc Encoder And Decoder For The Ieee802.11Ad Standard

IEEE802.11ad, the new generation ofWLAN technical standard that is proposed in early2013, is seen as a promising way to implement the HD audio and video signal transmission within the house. It not only brings a complete solution for the family multimedia applications, but also lays a solid foundation for the coming of Intelligent Home Furnishing and Internet of things. Low Density Parity Check(LDPC) code is a class of powerful error correcting code which can provide about8dB gain. Besides, due to its low decoding complexity and high throughput, LDPC is always called as a good code that performs closely to Shannon limit. Recently, LDPC has become another hot topic in the field of channel coding after Turbo code.This paper is mainly focused on the application research of LDPC in the latest WLAN protocol, IEEE802.11ad.The research is summarized as follows.Firstly, we study the background and main technologies of IEEE802.11ad. The standard is introduced from both system and physical layers, mainly including the scheme illustrations of transmitter and receiver, detail description of physical layer features and summarization of important characteristics and key techniques of IEEE802.11ad.Secondly, we conduct the research and implementation of two kinds of LDPC encoder. One encoder, QC-LDPC, is designed according to the H-matrix features in IEEE802.11ad and realized using FPGA. Based on this encoder, another encoder, π-rotated LDPC encoder is studied and proposed. The design, simulation and FPGA implementation of π-rotated LDPC encoder are involved in this paper.Thirdly, LDPC decoding algorithm is studied and implemented according to IEEE802.11ad requirements. Using detailed simulation and performance comparison of six LDPC decoding algorithms, we finally choose Normalized Min-Sum as our decoding algorithm in hardware implementtation. Corresponding parameter values are also decided and set using simulations. Then we analyze the characteristics of LDPC H-matrix in IEEE802.11ad standard, and propose a novel and efficient LDPC decoding structure based on FPGA.Finally, we test and analyze the performance of LDPC coder in the standard. As a conclusion, we verify the correctness of the LDPC coder, and provide a report about the utilization of hardware resources. This report demonstrates and introduces the whole performance of the coder.The main research method and progress are listed as below:The first step is literature research. In the early stage, we investigate the coding rational, decoding algorithm and structures of LDPC code. Based on the research results, we select an appropriate encoder and decoder algorithm for the standard.The second one is Matlab and C/C++simulation. According to the early literature, we conduct float-point simulation using Matlab and then fixed-point simulation using C/C++. The results of float-point simulation are analyzed for the later algorithm selection and scaling.The last step is FPGA implementation and testing. For the selected algorithm and structure, we conduct the hardware implementation using FPGA. Verilog code is prepared for the implementation and test of LDPC decoder on Virtex-7FPGA.