System-Level Design And Modeling For12Bit High Speed DAC

DAC is an essential interface component between the digital and analogcircuit. Recently, with the development of high-definition digital video andwireless communication, et al., higher requirement of speed and precision of DACis put forward. The purpose of system-level design is to analyze the relationshipbetween the design specifications and circuit parameters so as to providetheoretical guidance for circuit design. In this way, the efficiency of circuit designcan be improved and the design cycle can be shortened. System-level design is thekey part of a high performance DAC design, which has an essential theoretical andpractical value.Firstly, several DAC architectures are analyzed and compared in the thesis,and then the segmented current steering DAC architecture is pointed out as asuitable one for both high speed and high resolution. In order to determine thesegmented ratio, different segmented structures of12bit current-steering DAC aremodeled, simulated and analyzed, whose key factors of DNL, INL, THD and thearea is considered comprehensively, and then the “9+3” segmented structure isobtained. In order to reduce the size and design complexity of the encoder circuitfurther, the re-segmentation of the9bit thermometer is also studied, and finally the“5+4+3” segmented structure is determined and the corresponding ideal model isbuilt by SIMULINK.On bias of these, the thesis focuses on the performance of DAC caused by thefinite output impedance and the matching errors of current sources, includinggradient error and random matching error, and at the same time, somecorresponding mathematical expressions are presented. Then these non-idealfactors are modeled by SIMULINK, and the correctness of the expressions isverified by simulation. Besides, some suggestions are also given on how to reducethe influence of these non-ideal errors, which are used to direct the circuit design.Finally, based on SMIC0.13μm3.3V CMOS technology, the key circuits of a12bit400MSPS current steering DAC using “5+4+3” architecture is designed,which include the current source circuit, the switch driver circuit and thesynchronous circuit, then the whole DAC is simulated by Cadence Spectre. It isclear from the simulation result that the DNL is0.216LSB, INL is0.251LSB, and the SFDR reaches83.5dB when the frequency of input digital sinusoidal signal is49.609375MHz and the sampling rate is400MHz, in addition, the settling time ofthe DAC is4.8ns and all of which meet the design specification requirements.