Ldpc Code Decoding Technology Research And The Fpga Implementation

LDPC codes, also known as low density parity check codes, are a kind of channel coding, and they are directly determined by the parity check matrix. The length of the codes is generally longer, but they also show high decoding performance. So LDPC codes are researched by more and more people. Under this background, a LDPC decoder in DVB-S2(Digital Video Broadcasting-Satellite2) standard is designed in this paper.Several construction methods of LDPC codes are analysized in the paper. A variety of coding methods of LDPC codes are researched, and the performance of these algorithms is compared. The encoding algorithm of LDPC codes in DVB-S2standard is studied in-depth, and this is to prepare for the design of LDPC decoder.Aiming at the design of LDPC decoder, the decoding process of BP algorithm and LLR BP algorithm is analysized in-depth. As LLR BP decoding algorithm has high complexity, the node information processing rules in the algorithm is simplified, and then the min-sum decoding algorithm that has lower complexity is gotten. In order to compensate the lost performance in the min-sum decoding algorithm, the normalization factor is adopted to improve the performance of min-sum decoding algorithm. It can be seen from the simulation results that the min-sum decoding algorithm can achieve almost similar performance with the BP decoding algorithm.As the degree of parallelism of LDPC codes in DVB-S2standard is360, when designing the structure of the decoder, the partially parallel structure with the degree of parallelism for360is choosed. In accordance with the decoding process of improved min-sum decoding algorithm, the structure of every module of the decoder is designed in detail. According to the node information processing rules in the algorithm, dual-port RAM and single-port RAM are used respectively when designing the message storage module of variable nodes and check nodes. And then a LDPC decoder in DVB-S2standard is designed finally.Aiming at hardware implementation of the decoder, the decoder for DVB-S2standard designed in the paper is synthesized and implemented on FPGA plarform. In order to prove that the decoder can work correctly, the decoder is simulated in Modelsim environment. And all these prove that the decoder designed in the paper can work correctly and meet the requirement of the DVB-S2standard. Since LDPC codes have got people’s attention in the field of channel coding, all kinds of research for LDPC codes have also been started. And the partially parallel structure and improved min-sum decoding algorithm adopted in the paper have a certain reference value for the research of LDPC decoder.