Research On TPC Coding And Decoding Algorithms And Implementation On FPGA

The optimization of communication system is closely related to life.Channel coding has been playing a good role in improving communication quality.Turbo product code?TPC?is a kind of forward error correction code with excellent performance.It has the characteristics of simple coding structure,relatively low decoding complexity and fast convergence rate of iterative decoding.So,after Turbo product code was proposed,it was widely adopted.At present,many achievements have been made in the research of TPC coding and decoding algorithm at home and abroad.Firstly,this thesis introduces the theoretical basis of coding at the theoretical level,discusses the current two-dimensional and three-dimensional coding structures,and analyzes and compares their subcodes.Then,the decoding theory is systematically elaborated,the advantages and disadvantages of hard decision and soft decision decoding are analyzed and compared,and the soft decision decoding algorithm with better decoding performance is mainly studied.Aiming at the problems of high decoding complexity and high decoding delay of existing decoders,some adjustments are made based on the traditional Chase-II serial iterative decoding algorithm.The simulation results of MATLAB show that the performance loss of the improved algorithm is less than 0.5dB at bit error rate.In order to achieve high-speed decoding,the hardware design of the decoder for two-dimensional TPC with row-column component codes?64,57,4?and extended Hamming codes is carried out on the platform of FPGA.The xc7k410t series chips of Xilinx company are selected to realize the modularization of each step of improving Chase serial iterative decoding algorithm,and the correctness of the designed circuit is verified by the behavioral level simulation.By using the joint simulation of Modelsim and ISE,the overall performance of the fixed-point quantized decoder is analyzed,which achieves the same effect as that of MATLAB decoding simulation.When the signal-to-noise ratio is 4.5dB,the bit error rate can reach the 10^-6 magnitude.Based on VPX architecture,the decoding sub-card designed in this paper is tested jointly.When the system clock is 200 MHz,the highest decoding rate is 26.14 Mbps.The results show that the improved algorithm and corresponding decoder design adopted in this thesis can meet the actual engineering requirements.