Power-driven Optimization Of NoC Interconnect Design With Low Swing Interconnect

As the semi-conductor technology scaling, more and more micro-processors and storage memories integrated on a single chip, this would induce the design complexity of SoC (System on Chip) increase. Conventional SoC design based on bus architecture in IC could not meet the future requirement of technology developing, and this would even limit the performance increase of system. Hence as a high performance structure of future nanometer level, NoC was proposed, and many recently research works has been focused on. In deep sub-micrometers technology, power consumption and delay of on-chip interconnects would increase while the technique scaling and feature size decreasing. Because the cross section area of interconnect decrease would induce the resistance of interconnect increase, the latency of interconnect would completely exceed the latency of transistor. Considering the on-chip communication could further increase, the most technique constraint of on-chip multicore processor development has been the power of on-chip communication. Though there have been many researches on this direction, power consumption of NoCs implemented with current techniques is still too high to meet the expected needs of future CMPs. In recently NoC design flow, singly pursuit the delay optimization would cause the exceedingly power consumption. Therefore in this thesis, low power NoC design is set as the target, and the on-chip communication latency is introduced as constraint to address the design concerns of on-chip interconnects. Through doing some research on problems such as high power consumption of on-chip communication in NoC, then looked up some documents, we explored related fields in this thesis. Research contents and achievements are concluded as follows:1. Power consumption of on-chip communicationDue to the transition on interconnects would lead to switch capacitor, there exist power enlargement concerns on on-chip interconnects. This might restrict the performance of NoCs if the power concerns have not been worked out. In practical application, the power concerns would bring about too large heat productivity, such as the too short cruising duration of mobile devices and too much energy consumption problems. There are three parts of power consumption in NoC:switch power, short circuit power and leakage power. Under deep sub-micrometer, power result from on-chip interconnect take a considerable part of the total power in NoC. Considering that switch power is most of total on-chip interconnects power, reduction of total power in NoC could be achieved by minimizing switch power. So in this thesis we reduce the total power of NoC through optimization of switch power of interconnects, and the low power design requirements of future CMP would be met.2. Recently work and research on low swing interconnectThe switch power of NoC is affected by voltage swing. Under the situation that there exists a lack of advanced technique and architecture to reduce the average length and fan-out, reduce the voltage swing is the best way to improve the energy efficient. Several kind of low swing techniques are introduced in this thesis, such as Conventional Level Converter (CLC), Pseudo Differential Interconnect (DIFF) and Symmetric Source-Follower Driver withz Level Converter (SSDLC), etc. However, these techniques show a wide variety of problems in efficiency, performance, robustness, and design complexity. Hence the Capacitively Driven Low Swing Interconnect is introduced and set a research focus in this thesis. By coupling a capacitor in transceiver, this technique decreased the voltage swing without a second power supply, and meanwhile achieved the power reduction. Otherwise, pre-emphasizes in driver side leads to bandwidth improvement while reducing the driver’s load. In this way, power and area of driver side is efficiently reduced. In this text, toward to CDLSI technique, under deep sub-micrometer, through Elmore model and single bit transition model, we respectively modeled the transceiver and receiver circuits on power and delay to analysis the performance of on-chip communication.3. Power-Delay optimization modelConsider the on-chip IP cores increasing, the number and length of global wire rises as a result of technology scaling in NoC design. To meet the design requirements, long interconnects are generally divided into a number of segments with repeaters or buffers. Repeaters and inter-repeater interconnects are usually optimized for performance of NoC. However, this would cause to significant enlargement on power consumption of on-chip communication, which is against to the purpose of this work. Some documents about conventional full swing interconnect are found after we do some research work on low power design and implementation of NoC. Yet there is not any optimization proposal for low swing interconnects in NoC design. As the structures of low swing interconnects are different from conventional full swing interconnects, the conventional optimization methodologies for full swing interconnect are not suited for low swing interconnects. Take advantages of CDLSI compared to other low swing interconnects into consideration, the power-delay optimization model for low swing interconnects is proposed based on CDLSI. Under the situation of optimal delay, this model could decrease the power consumption with a delay penalty. The simulation results show that the implementation of proposed model would efficiently reduce the power consumption of on-chip interconnect with little delay penalty.4. Power-driven optimization flowLatency as one of the most important things which judge the performance of NoCneeds to be focused in NoC design. Current NoC design flow optimization is directly work for the full swing interconnects, which means to optimize the latency of interconnect. As the power concerns became the most limitation of NoC performance, delay optimal design goes against to the low power NoC implementation. Hence this text in view of power and delay of on-chip interconnect, unite the current NoC design flow, and use a power-driven optimization algorithmbased on proposed optimization model to further optimize the power consumption under delay constraints. By taking the latency of full voltage swing interconnects as a delay constraint, this algorithm iteratively optimizes the power of NoC. The simulation results show that the proposed algorithm could significantly reduce the power consumption of on-chip communication of NoC under delay constraints.